mthca_cmd.c

h内核

	if (ret || status)
		return ret;

	/*
	 * Arbel page size is always 4 KB; round up number of system
	 * pages needed.
	 */
	*aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);

	return 0;
}

int mthca_SW2HW_MPT(struct mthca_dev *dev, void *mpt_entry,
		    int mpt_index, u8 *status)
{
	dma_addr_t indma;
	int err;

	indma = pci_map_single(dev->pdev, mpt_entry,
			       MTHCA_MPT_ENTRY_SIZE,
			       PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(indma))
		return -ENOMEM;

	err = mthca_cmd(dev, indma, mpt_index, 0, CMD_SW2HW_MPT,
			CMD_TIME_CLASS_B, status);

	pci_unmap_single(dev->pdev, indma,
			 MTHCA_MPT_ENTRY_SIZE, PCI_DMA_TODEVICE);
	return err;
}

int mthca_HW2SW_MPT(struct mthca_dev *dev, void *mpt_entry,
		    int mpt_index, u8 *status)
{
	dma_addr_t outdma = 0;
	int err;

	if (mpt_entry) {
		outdma = pci_map_single(dev->pdev, mpt_entry,
					MTHCA_MPT_ENTRY_SIZE,
					PCI_DMA_FROMDEVICE);
		if (pci_dma_mapping_error(outdma))
			return -ENOMEM;
	}

	err = mthca_cmd_box(dev, 0, outdma, mpt_index, !mpt_entry,
			    CMD_HW2SW_MPT,
			    CMD_TIME_CLASS_B, status);

	if (mpt_entry)
		pci_unmap_single(dev->pdev, outdma,
				 MTHCA_MPT_ENTRY_SIZE,
				 PCI_DMA_FROMDEVICE);
	return err;
}

int mthca_WRITE_MTT(struct mthca_dev *dev, u64 *mtt_entry,
		    int num_mtt, u8 *status)
{
	dma_addr_t indma;
	int err;

	indma = pci_map_single(dev->pdev, mtt_entry,
			       (num_mtt + 2) * 8,
			       PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(indma))
		return -ENOMEM;

	err = mthca_cmd(dev, indma, num_mtt, 0, CMD_WRITE_MTT,
			CMD_TIME_CLASS_B, status);

	pci_unmap_single(dev->pdev, indma,
			 (num_mtt + 2) * 8, PCI_DMA_TODEVICE);
	return err;
}

int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
		 int eq_num, u8 *status)
{
	mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
		  unmap ? "Clearing" : "Setting",
		  (unsigned long long) event_mask, eq_num);
	return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
			 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
}

int mthca_SW2HW_EQ(struct mthca_dev *dev, void *eq_context,
		   int eq_num, u8 *status)
{
	dma_addr_t indma;
	int err;

	indma = pci_map_single(dev->pdev, eq_context,
			       MTHCA_EQ_CONTEXT_SIZE,
			       PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(indma))
		return -ENOMEM;

	err = mthca_cmd(dev, indma, eq_num, 0, CMD_SW2HW_EQ,
			CMD_TIME_CLASS_A, status);

	pci_unmap_single(dev->pdev, indma,
			 MTHCA_EQ_CONTEXT_SIZE, PCI_DMA_TODEVICE);
	return err;
}

int mthca_HW2SW_EQ(struct mthca_dev *dev, void *eq_context,
		   int eq_num, u8 *status)
{
	dma_addr_t outdma = 0;
	int err;

	outdma = pci_map_single(dev->pdev, eq_context,
				MTHCA_EQ_CONTEXT_SIZE,
				PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(outdma))
		return -ENOMEM;

	err = mthca_cmd_box(dev, 0, outdma, eq_num, 0,
			    CMD_HW2SW_EQ,
			    CMD_TIME_CLASS_A, status);

	pci_unmap_single(dev->pdev, outdma,
			 MTHCA_EQ_CONTEXT_SIZE,
			 PCI_DMA_FROMDEVICE);
	return err;
}

int mthca_SW2HW_CQ(struct mthca_dev *dev, void *cq_context,
		   int cq_num, u8 *status)
{
	dma_addr_t indma;
	int err;

	indma = pci_map_single(dev->pdev, cq_context,
			       MTHCA_CQ_CONTEXT_SIZE,
			       PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(indma))
		return -ENOMEM;

	err = mthca_cmd(dev, indma, cq_num, 0, CMD_SW2HW_CQ,
			CMD_TIME_CLASS_A, status);

	pci_unmap_single(dev->pdev, indma,
			 MTHCA_CQ_CONTEXT_SIZE, PCI_DMA_TODEVICE);
	return err;
}

int mthca_HW2SW_CQ(struct mthca_dev *dev, void *cq_context,
		   int cq_num, u8 *status)
{
	dma_addr_t outdma = 0;
	int err;

	outdma = pci_map_single(dev->pdev, cq_context,
				MTHCA_CQ_CONTEXT_SIZE,
				PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(outdma))
		return -ENOMEM;

	err = mthca_cmd_box(dev, 0, outdma, cq_num, 0,
			    CMD_HW2SW_CQ,
			    CMD_TIME_CLASS_A, status);

	pci_unmap_single(dev->pdev, outdma,
			 MTHCA_CQ_CONTEXT_SIZE,
			 PCI_DMA_FROMDEVICE);
	return err;
}

int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
		    int is_ee, void *qp_context, u32 optmask,
		    u8 *status)
{
	static const u16 op[] = {
		[MTHCA_TRANS_RST2INIT]  = CMD_RST2INIT_QPEE,
		[MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE,
		[MTHCA_TRANS_INIT2RTR]  = CMD_INIT2RTR_QPEE,
		[MTHCA_TRANS_RTR2RTS]   = CMD_RTR2RTS_QPEE,
		[MTHCA_TRANS_RTS2RTS]   = CMD_RTS2RTS_QPEE,
		[MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE,
		[MTHCA_TRANS_ANY2ERR]   = CMD_2ERR_QPEE,
		[MTHCA_TRANS_RTS2SQD]   = CMD_RTS2SQD_QPEE,
		[MTHCA_TRANS_SQD2SQD]   = CMD_SQD2SQD_QPEE,
		[MTHCA_TRANS_SQD2RTS]   = CMD_SQD2RTS_QPEE,
		[MTHCA_TRANS_ANY2RST]   = CMD_ERR2RST_QPEE
	};
	u8 op_mod = 0;

	dma_addr_t indma;
	int err;

	if (trans < 0 || trans >= ARRAY_SIZE(op))
		return -EINVAL;

	if (trans == MTHCA_TRANS_ANY2RST) {
		indma  = 0;
		op_mod = 3;	/* don't write outbox, any->reset */

		/* For debugging */
		qp_context = pci_alloc_consistent(dev->pdev, MTHCA_QP_CONTEXT_SIZE,
						  &indma);
		op_mod = 2;	/* write outbox, any->reset */
	} else {
		indma = pci_map_single(dev->pdev, qp_context,
				       MTHCA_QP_CONTEXT_SIZE,
				       PCI_DMA_TODEVICE);
		if (pci_dma_mapping_error(indma))
			return -ENOMEM;

		if (0) {
			int i;
			mthca_dbg(dev, "Dumping QP context:\n");
			printk(" %08x\n", be32_to_cpup(qp_context));
			for (i = 0; i < 0x100 / 4; ++i) {
				if (i % 8 == 0)
					printk("[%02x] ", i * 4);
				printk(" %08x", be32_to_cpu(((u32 *) qp_context)[i + 2]));
				if ((i + 1) % 8 == 0)
					printk("\n");
			}
		}
	}

	if (trans == MTHCA_TRANS_ANY2RST) {
		err = mthca_cmd_box(dev, 0, indma, (!!is_ee << 24) | num,
				    op_mod, op[trans], CMD_TIME_CLASS_C, status);

		if (0) {
			int i;
			mthca_dbg(dev, "Dumping QP context:\n");
			printk(" %08x\n", be32_to_cpup(qp_context));
			for (i = 0; i < 0x100 / 4; ++i) {
				if (i % 8 == 0)
					printk("[%02x] ", i * 4);
				printk(" %08x", be32_to_cpu(((u32 *) qp_context)[i + 2]));
				if ((i + 1) % 8 == 0)
					printk("\n");
			}
		}

	} else
		err = mthca_cmd(dev, indma, (!!is_ee << 24) | num,
				op_mod, op[trans], CMD_TIME_CLASS_C, status);

	if (trans != MTHCA_TRANS_ANY2RST)
		pci_unmap_single(dev->pdev, indma,
				 MTHCA_QP_CONTEXT_SIZE, PCI_DMA_TODEVICE);
	else
		pci_free_consistent(dev->pdev, MTHCA_QP_CONTEXT_SIZE,
				    qp_context, indma);
	return err;
}

int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
		   void *qp_context, u8 *status)
{
	dma_addr_t outdma = 0;
	int err;

	outdma = pci_map_single(dev->pdev, qp_context,
				MTHCA_QP_CONTEXT_SIZE,
				PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(outdma))
		return -ENOMEM;

	err = mthca_cmd_box(dev, 0, outdma, (!!is_ee << 24) | num, 0,
			    CMD_QUERY_QPEE,
			    CMD_TIME_CLASS_A, status);

	pci_unmap_single(dev->pdev, outdma,
			 MTHCA_QP_CONTEXT_SIZE,
			 PCI_DMA_FROMDEVICE);
	return err;
}

int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
			  u8 *status)
{
	u8 op_mod;

	switch (type) {
	case IB_QPT_SMI:
		op_mod = 0;
		break;
	case IB_QPT_GSI:
		op_mod = 1;
		break;
	case IB_QPT_RAW_IPV6:
		op_mod = 2;
		break;
	case IB_QPT_RAW_ETY:
		op_mod = 3;
		break;
	default:
		return -EINVAL;
	}

	return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
			 CMD_TIME_CLASS_B, status);
}

int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
		  int port, struct ib_wc* in_wc, struct ib_grh* in_grh,
		  void *in_mad, void *response_mad, u8 *status)
{
	void *box;
	dma_addr_t dma;
	int err;
	u32 in_modifier = port;
	u8 op_modifier = 0;

#define MAD_IFC_BOX_SIZE      0x400
#define MAD_IFC_MY_QPN_OFFSET 0x100
#define MAD_IFC_RQPN_OFFSET   0x104
#define MAD_IFC_SL_OFFSET     0x108
#define MAD_IFC_G_PATH_OFFSET 0x109
#define MAD_IFC_RLID_OFFSET   0x10a
#define MAD_IFC_PKEY_OFFSET   0x10e
#define MAD_IFC_GRH_OFFSET    0x140

	box = pci_alloc_consistent(dev->pdev, MAD_IFC_BOX_SIZE, &dma);
	if (!box)
		return -ENOMEM;

	memcpy(box, in_mad, 256);

	/*
	 * Key check traps can't be generated unless we have in_wc to
	 * tell us where to send the trap.
	 */
	if (ignore_mkey || !in_wc)
		op_modifier |= 0x1;
	if (ignore_bkey || !in_wc)
		op_modifier |= 0x2;

	if (in_wc) {
		u8 val;

		memset(box + 256, 0, 256);

		MTHCA_PUT(box, in_wc->qp_num, 	  MAD_IFC_MY_QPN_OFFSET);
		MTHCA_PUT(box, in_wc->src_qp, 	  MAD_IFC_RQPN_OFFSET);

		val = in_wc->sl << 4;
		MTHCA_PUT(box, val,               MAD_IFC_SL_OFFSET);

		val = in_wc->dlid_path_bits |
			(in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
		MTHCA_PUT(box, val,               MAD_IFC_GRH_OFFSET);

		MTHCA_PUT(box, in_wc->slid,       MAD_IFC_RLID_OFFSET);
		MTHCA_PUT(box, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);

		if (in_grh)
			memcpy((u8 *) box + MAD_IFC_GRH_OFFSET, in_grh, 40);

		op_modifier |= 0x10;

		in_modifier |= in_wc->slid << 16;
	}

	err = mthca_cmd_box(dev, dma, dma + 512, in_modifier, op_modifier,
			    CMD_MAD_IFC, CMD_TIME_CLASS_C, status);

	if (!err && !*status)
		memcpy(response_mad, box + 512, 256);

	pci_free_consistent(dev->pdev, MAD_IFC_BOX_SIZE, box, dma);
	return err;
}

int mthca_READ_MGM(struct mthca_dev *dev, int index, void *mgm,
		   u8 *status)
{
	dma_addr_t outdma = 0;
	int err;

	outdma = pci_map_single(dev->pdev, mgm,
				MTHCA_MGM_ENTRY_SIZE,
				PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(outdma))
		return -ENOMEM;

	err = mthca_cmd_box(dev, 0, outdma, index, 0,
			    CMD_READ_MGM,
			    CMD_TIME_CLASS_A, status);

	pci_unmap_single(dev->pdev, outdma,
			 MTHCA_MGM_ENTRY_SIZE,
			 PCI_DMA_FROMDEVICE);
	return err;
}

int mthca_WRITE_MGM(struct mthca_dev *dev, int index, void *mgm,
		    u8 *status)
{
	dma_addr_t indma;
	int err;

	indma = pci_map_single(dev->pdev, mgm,
			       MTHCA_MGM_ENTRY_SIZE,
			       PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(indma))
		return -ENOMEM;

	err = mthca_cmd(dev, indma, index, 0, CMD_WRITE_MGM,
			CMD_TIME_CLASS_A, status);

	pci_unmap_single(dev->pdev, indma,
			 MTHCA_MGM_ENTRY_SIZE, PCI_DMA_TODEVICE);
	return err;
}

int mthca_MGID_HASH(struct mthca_dev *dev, void *gid, u16 *hash,
		    u8 *status)
{
	dma_addr_t indma;
	u64 imm;
	int err;

	indma = pci_map_single(dev->pdev, gid, 16, PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(indma))
		return -ENOMEM;

	err = mthca_cmd_imm(dev, indma, &imm, 0, 0, CMD_MGID_HASH,
			    CMD_TIME_CLASS_A, status);
	*hash = imm;

	pci_unmap_single(dev->pdev, indma, 16, PCI_DMA_TODEVICE);
	return err;
}

int mthca_NOP(struct mthca_dev *dev, u8 *status)
{
	return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
}