mthca_cmd.c

h内核

	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
	dev_lim->reserved_eecs = 1 << (field & 0xf);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
	dev_lim->max_eecs = 1 << (field & 0x1f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
	dev_lim->max_cq_sz = 1 << field;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
	dev_lim->reserved_cqs = 1 << (field & 0xf);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
	dev_lim->max_cqs = 1 << (field & 0x1f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
	dev_lim->max_mpts = 1 << (field & 0x3f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
	dev_lim->reserved_eqs = 1 << (field & 0xf);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
	dev_lim->max_eqs = 1 << (field & 0x7);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
	dev_lim->reserved_mtts = 1 << (field >> 4);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
	dev_lim->max_mrw_sz = 1 << field;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
	dev_lim->reserved_mrws = 1 << (field & 0xf);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
	dev_lim->max_mtt_seg = 1 << (field & 0x3f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
	dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
	dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
	dev_lim->max_rdma_global = 1 << (field & 0x3f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
	dev_lim->local_ca_ack_delay = field & 0x1f;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
	dev_lim->max_mtu        = field >> 4;
	dev_lim->max_port_width = field & 0xf;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
	dev_lim->max_vl    = field >> 4;
	dev_lim->num_ports = field & 0xf;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
	dev_lim->max_gids = 1 << (field & 0xf);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
	dev_lim->max_pkeys = 1 << (field & 0xf);
	MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
	dev_lim->reserved_uars = field >> 4;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
	dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
	dev_lim->min_page_sz = 1 << field;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
	dev_lim->max_sg = field;

	MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
	dev_lim->max_desc_sz = size;

	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
	dev_lim->max_qp_per_mcg = 1 << field;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
	dev_lim->reserved_mgms = field & 0xf;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
	dev_lim->max_mcgs = 1 << field;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
	dev_lim->reserved_pds = field >> 4;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
	dev_lim->max_pds = 1 << (field & 0x3f);
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
	dev_lim->reserved_rdds = field >> 4;
	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
	dev_lim->max_rdds = 1 << (field & 0x3f);

	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
	dev_lim->eec_entry_sz = size;
	MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
	dev_lim->qpc_entry_sz = size;
	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
	dev_lim->eeec_entry_sz = size;
	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
	dev_lim->eqpc_entry_sz = size;
	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
	dev_lim->eqc_entry_sz = size;
	MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
	dev_lim->cqc_entry_sz = size;
	MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
	dev_lim->srq_entry_sz = size;
	MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
	dev_lim->uar_scratch_entry_sz = size;

	mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
		  dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
	mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
		  dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
	mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
		  dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
	mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
		  dev_lim->reserved_mrws, dev_lim->reserved_mtts);
	mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
		  dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
	mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
		  dev_lim->max_pds, dev_lim->reserved_mgms);

	mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);

	if (dev->hca_type == ARBEL_NATIVE) {
		MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
		dev_lim->hca.arbel.resize_srq = field & 1;
		MTHCA_GET(size, outbox, QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET);
		dev_lim->mtt_seg_sz = size;
		MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
		dev_lim->mpt_entry_sz = size;
		MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
		dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
		MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
			  QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
		MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
			  QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
		MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
		dev_lim->hca.arbel.lam_required = field & 1;
		MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
			  QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);

		if (dev_lim->hca.arbel.bmme_flags & 1)
			mthca_dbg(dev, "Base MM extensions: yes "
				  "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
				  dev_lim->hca.arbel.bmme_flags,
				  dev_lim->hca.arbel.max_pbl_sz,
				  dev_lim->hca.arbel.reserved_lkey);
		else
			mthca_dbg(dev, "Base MM extensions: no\n");

		mthca_dbg(dev, "Max ICM size %lld MB\n",
			  (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
	} else {
		MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
		dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
		dev_lim->mtt_seg_sz   = MTHCA_MTT_SEG_SIZE;
		dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
	}

out:
	pci_free_consistent(dev->pdev, QUERY_DEV_LIM_OUT_SIZE, outbox, outdma);
	return err;
}

int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
			struct mthca_adapter *adapter, u8 *status)
{
	u32 *outbox;
	dma_addr_t outdma;
	int err;

#define QUERY_ADAPTER_OUT_SIZE             0x100
#define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
#define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
#define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
#define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10

	outbox = pci_alloc_consistent(dev->pdev, QUERY_ADAPTER_OUT_SIZE, &outdma);
	if (!outbox)
		return -ENOMEM;

	err = mthca_cmd_box(dev, 0, outdma, 0, 0, CMD_QUERY_ADAPTER,
			    CMD_TIME_CLASS_A, status);

	if (err)
		goto out;

	MTHCA_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET);
	MTHCA_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET);
	MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
	MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);

out:
	pci_free_consistent(dev->pdev, QUERY_DEV_LIM_OUT_SIZE, outbox, outdma);
	return err;
}

int mthca_INIT_HCA(struct mthca_dev *dev,
		   struct mthca_init_hca_param *param,
		   u8 *status)
{
	u32 *inbox;
	dma_addr_t indma;
	int err;

#define INIT_HCA_IN_SIZE             	 0x200
#define INIT_HCA_FLAGS_OFFSET        	 0x014
#define INIT_HCA_QPC_OFFSET          	 0x020
#define  INIT_HCA_QPC_BASE_OFFSET    	 (INIT_HCA_QPC_OFFSET + 0x10)
#define  INIT_HCA_LOG_QP_OFFSET      	 (INIT_HCA_QPC_OFFSET + 0x17)
#define  INIT_HCA_EEC_BASE_OFFSET    	 (INIT_HCA_QPC_OFFSET + 0x20)
#define  INIT_HCA_LOG_EEC_OFFSET     	 (INIT_HCA_QPC_OFFSET + 0x27)
#define  INIT_HCA_SRQC_BASE_OFFSET   	 (INIT_HCA_QPC_OFFSET + 0x28)
#define  INIT_HCA_LOG_SRQ_OFFSET     	 (INIT_HCA_QPC_OFFSET + 0x2f)
#define  INIT_HCA_CQC_BASE_OFFSET    	 (INIT_HCA_QPC_OFFSET + 0x30)
#define  INIT_HCA_LOG_CQ_OFFSET      	 (INIT_HCA_QPC_OFFSET + 0x37)
#define  INIT_HCA_EQPC_BASE_OFFSET   	 (INIT_HCA_QPC_OFFSET + 0x40)
#define  INIT_HCA_EEEC_BASE_OFFSET   	 (INIT_HCA_QPC_OFFSET + 0x50)
#define  INIT_HCA_EQC_BASE_OFFSET    	 (INIT_HCA_QPC_OFFSET + 0x60)
#define  INIT_HCA_LOG_EQ_OFFSET      	 (INIT_HCA_QPC_OFFSET + 0x67)
#define  INIT_HCA_RDB_BASE_OFFSET    	 (INIT_HCA_QPC_OFFSET + 0x70)
#define INIT_HCA_UDAV_OFFSET         	 0x0b0
#define  INIT_HCA_UDAV_LKEY_OFFSET   	 (INIT_HCA_UDAV_OFFSET + 0x0)
#define  INIT_HCA_UDAV_PD_OFFSET     	 (INIT_HCA_UDAV_OFFSET + 0x4)
#define INIT_HCA_MCAST_OFFSET        	 0x0c0
#define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
#define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
#define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
#define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
#define INIT_HCA_TPT_OFFSET              0x0f0
#define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
#define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
#define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
#define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
#define INIT_HCA_UAR_OFFSET              0x120
#define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
#define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
#define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
#define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
#define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
#define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)

	inbox = pci_alloc_consistent(dev->pdev, INIT_HCA_IN_SIZE, &indma);
	if (!inbox)
		return -ENOMEM;

	memset(inbox, 0, INIT_HCA_IN_SIZE);

#if defined(__LITTLE_ENDIAN)
	*(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
#elif defined(__BIG_ENDIAN)
	*(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
#else
#error Host endianness not defined
#endif
	/* Check port for UD address vector: */
	*(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);

	/* We leave wqe_quota, responder_exu, etc as 0 (default) */

	/* QPC/EEC/CQC/EQC/RDB attributes */

	MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
	MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
	MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
	MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
	MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
	MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);

	/* UD AV attributes */

	/* multicast attributes */

	MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
	MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
	MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
	MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);

	/* TPT attributes */

	MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
	if (dev->hca_type != ARBEL_NATIVE)
		MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
	MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
	MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);

	/* UAR attributes */
	{
		u8 uar_page_sz = PAGE_SHIFT - 12;
		MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
	}

	MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);

	if (dev->hca_type == ARBEL_NATIVE) {
		MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
		MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
		MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
	}

	err = mthca_cmd(dev, indma, 0, 0, CMD_INIT_HCA,
			HZ, status);

	pci_free_consistent(dev->pdev, INIT_HCA_IN_SIZE, inbox, indma);
	return err;
}

int mthca_INIT_IB(struct mthca_dev *dev,
		  struct mthca_init_ib_param *param,
		  int port, u8 *status)
{
	u32 *inbox;
	dma_addr_t indma;
	int err;
	u32 flags;

#define INIT_IB_IN_SIZE          56
#define INIT_IB_FLAGS_OFFSET     0x00
#define INIT_IB_FLAG_SIG         (1 << 18)
#define INIT_IB_FLAG_NG          (1 << 17)
#define INIT_IB_FLAG_G0          (1 << 16)
#define INIT_IB_FLAG_1X          (1 << 8)
#define INIT_IB_FLAG_4X          (1 << 9)
#define INIT_IB_FLAG_12X         (1 << 11)
#define INIT_IB_VL_SHIFT         4
#define INIT_IB_MTU_SHIFT        12
#define INIT_IB_MAX_GID_OFFSET   0x06
#define INIT_IB_MAX_PKEY_OFFSET  0x0a
#define INIT_IB_GUID0_OFFSET     0x10
#define INIT_IB_NODE_GUID_OFFSET 0x18
#define INIT_IB_SI_GUID_OFFSET   0x20

	inbox = pci_alloc_consistent(dev->pdev, INIT_IB_IN_SIZE, &indma);
	if (!inbox)
		return -ENOMEM;

	memset(inbox, 0, INIT_IB_IN_SIZE);

	flags = 0;
	flags |= param->enable_1x     ? INIT_IB_FLAG_1X  : 0;
	flags |= param->enable_4x     ? INIT_IB_FLAG_4X  : 0;
	flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
	flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
	flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
	flags |= param->vl_cap << INIT_IB_VL_SHIFT;
	flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
	MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);

	MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
	MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
	MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
	MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
	MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);

	err = mthca_cmd(dev, indma, port, 0, CMD_INIT_IB,
			CMD_TIME_CLASS_A, status);

	pci_free_consistent(dev->pdev, INIT_HCA_IN_SIZE, inbox, indma);
	return err;
}

int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
{
	return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
}

int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
{
	return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
}

int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
		 int port, u8 *status)
{
	u32 *inbox;
	dma_addr_t indma;
	int err;
	u32 flags = 0;

#define SET_IB_IN_SIZE         0x40
#define SET_IB_FLAGS_OFFSET    0x00
#define SET_IB_FLAG_SIG        (1 << 18)
#define SET_IB_FLAG_RQK        (1 <<  0)
#define SET_IB_CAP_MASK_OFFSET 0x04
#define SET_IB_SI_GUID_OFFSET  0x08

	inbox = pci_alloc_consistent(dev->pdev, SET_IB_IN_SIZE, &indma);
	if (!inbox)
		return -ENOMEM;

	memset(inbox, 0, SET_IB_IN_SIZE);

	flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
	flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
	MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);

	MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
	MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);

	err = mthca_cmd(dev, indma, port, 0, CMD_SET_IB,
			CMD_TIME_CLASS_B, status);

	pci_free_consistent(dev->pdev, INIT_HCA_IN_SIZE, inbox, indma);
	return err;
}

int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
{
	return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
}

int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
{
	u64 *inbox;
	dma_addr_t indma;
	int err;

	inbox = pci_alloc_consistent(dev->pdev, 16, &indma);
	if (!inbox)
		return -ENOMEM;

	inbox[0] = cpu_to_be64(virt);
	inbox[1] = cpu_to_be64(dma_addr | (PAGE_SHIFT - 12));

	err = mthca_cmd(dev, indma, 1, 0, CMD_MAP_ICM, CMD_TIME_CLASS_B, status);

	pci_free_consistent(dev->pdev, 16, inbox, indma);

	if (!err)
		mthca_dbg(dev, "Mapped page at %llx for ICM.\n",
			  (unsigned long long) virt);

	return err;
}

int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
{
	return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
}

int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
{
	return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
}

int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
{
	return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
}

int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
		       u8 *status)
{
	int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
				CMD_TIME_CLASS_A, status);