📄 mpi_cnfg.h
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/* values for the BiosOptions field */#define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)#define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)#define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)#define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)/* values for the IOCSettings field */#define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)#define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)#define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)#define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)#define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)#define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)#define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)#define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)#define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)#define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)#define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)#define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)/* values for the DeviceSettings field */#define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)#define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)#define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)#define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)/***************************************************************************** SCSI Port Config Pages****************************************************************************/typedef struct _CONFIG_PAGE_SCSI_PORT_0{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 Capabilities; /* 04h */ U32 PhysicalInterface; /* 08h */} fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01)#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)#define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)#define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)#define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)#define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)#define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)#define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)#define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)#define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)#define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)#define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \ >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ )#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)#define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \ >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ )#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)typedef struct _CONFIG_PAGE_SCSI_PORT_1{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 Configuration; /* 04h */ U32 OnBusTimerValue; /* 08h */ U8 TargetConfig; /* 0Ch */ U8 Reserved1; /* 0Dh */ U16 IDConfig; /* 0Eh */} fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)/* Configuration values */#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)#define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)/* TargetConfig values */#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)#define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)typedef struct _MPI_DEVICE_INFO{ U8 Timeout; /* 00h */ U8 SyncFactor; /* 01h */ U16 DeviceFlags; /* 02h */} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;typedef struct _CONFIG_PAGE_SCSI_PORT_2{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 PortFlags; /* 04h */ U32 PortSettings; /* 08h */ MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */} fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)/* PortFlags values */#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)#define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)#define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)#define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)#define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)/* PortSettings values */#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)#define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)#define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)#define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)#define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)/***************************************************************************** SCSI Target Device Config Pages****************************************************************************/typedef struct _CONFIG_PAGE_SCSI_DEVICE_0{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 NegotiatedParameters; /* 04h */ U32 Information; /* 08h */} fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03)#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)typedef struct _CONFIG_PAGE_SCSI_DEVICE_1{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 RequestedParameters; /* 04h */ U32 Reserved; /* 08h */ U32 Configuration; /* 0Ch */} fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04)#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)#define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)#define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)typedef struct _CONFIG_PAGE_SCSI_DEVICE_2{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 DomainValidation; /* 04h */ U32 ParityPipeSelect; /* 08h */ U32 DataPipeSelect; /* 0Ch */} fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)⌨️ 快捷键说明
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