traps.c

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 */
struct cheetah_err_info {
/*0x00*/u64 afsr;
/*0x08*/u64 afar;

	/* D-cache state */
/*0x10*/u64 dcache_data[4];	/* The actual data	*/
/*0x30*/u64 dcache_index;	/* D-cache index	*/
/*0x38*/u64 dcache_tag;		/* D-cache tag/valid	*/
/*0x40*/u64 dcache_utag;	/* D-cache microtag	*/
/*0x48*/u64 dcache_stag;	/* D-cache snooptag	*/

	/* I-cache state */
/*0x50*/u64 icache_data[8];	/* The actual insns + predecode	*/
/*0x90*/u64 icache_index;	/* I-cache index	*/
/*0x98*/u64 icache_tag;		/* I-cache phys tag	*/
/*0xa0*/u64 icache_utag;	/* I-cache microtag	*/
/*0xa8*/u64 icache_stag;	/* I-cache snooptag	*/
/*0xb0*/u64 icache_upper;	/* I-cache upper-tag	*/
/*0xb8*/u64 icache_lower;	/* I-cache lower-tag	*/

	/* E-cache state */
/*0xc0*/u64 ecache_data[4];	/* 32 bytes from staging registers */
/*0xe0*/u64 ecache_index;	/* E-cache index	*/
/*0xe8*/u64 ecache_tag;		/* E-cache tag/state	*/

/*0xf0*/u64 __pad[32 - 30];
};
#define CHAFSR_INVALID		((u64)-1L)

/* This table is ordered in priority of errors and matches the
 * AFAR overwrite policy as well.
 */

struct afsr_error_table {
	unsigned long mask;
	const char *name;
};

static const char CHAFSR_PERR_msg[] =
	"System interface protocol error";
static const char CHAFSR_IERR_msg[] =
	"Internal processor error";
static const char CHAFSR_ISAP_msg[] =
	"System request parity error on incoming addresss";
static const char CHAFSR_UCU_msg[] =
	"Uncorrectable E-cache ECC error for ifetch/data";
static const char CHAFSR_UCC_msg[] =
	"SW Correctable E-cache ECC error for ifetch/data";
static const char CHAFSR_UE_msg[] =
	"Uncorrectable system bus data ECC error for read";
static const char CHAFSR_EDU_msg[] =
	"Uncorrectable E-cache ECC error for stmerge/blkld";
static const char CHAFSR_EMU_msg[] =
	"Uncorrectable system bus MTAG error";
static const char CHAFSR_WDU_msg[] =
	"Uncorrectable E-cache ECC error for writeback";
static const char CHAFSR_CPU_msg[] =
	"Uncorrectable ECC error for copyout";
static const char CHAFSR_CE_msg[] =
	"HW corrected system bus data ECC error for read";
static const char CHAFSR_EDC_msg[] =
	"HW corrected E-cache ECC error for stmerge/blkld";
static const char CHAFSR_EMC_msg[] =
	"HW corrected system bus MTAG ECC error";
static const char CHAFSR_WDC_msg[] =
	"HW corrected E-cache ECC error for writeback";
static const char CHAFSR_CPC_msg[] =
	"HW corrected ECC error for copyout";
static const char CHAFSR_TO_msg[] =
	"Unmapped error from system bus";
static const char CHAFSR_BERR_msg[] =
	"Bus error response from system bus";
static const char CHAFSR_IVC_msg[] =
	"HW corrected system bus data ECC error for ivec read";
static const char CHAFSR_IVU_msg[] =
	"Uncorrectable system bus data ECC error for ivec read";
static struct afsr_error_table __cheetah_error_table[] = {
	{	CHAFSR_PERR,	CHAFSR_PERR_msg		},
	{	CHAFSR_IERR,	CHAFSR_IERR_msg		},
	{	CHAFSR_ISAP,	CHAFSR_ISAP_msg		},
	{	CHAFSR_UCU,	CHAFSR_UCU_msg		},
	{	CHAFSR_UCC,	CHAFSR_UCC_msg		},
	{	CHAFSR_UE,	CHAFSR_UE_msg		},
	{	CHAFSR_EDU,	CHAFSR_EDU_msg		},
	{	CHAFSR_EMU,	CHAFSR_EMU_msg		},
	{	CHAFSR_WDU,	CHAFSR_WDU_msg		},
	{	CHAFSR_CPU,	CHAFSR_CPU_msg		},
	{	CHAFSR_CE,	CHAFSR_CE_msg		},
	{	CHAFSR_EDC,	CHAFSR_EDC_msg		},
	{	CHAFSR_EMC,	CHAFSR_EMC_msg		},
	{	CHAFSR_WDC,	CHAFSR_WDC_msg		},
	{	CHAFSR_CPC,	CHAFSR_CPC_msg		},
	{	CHAFSR_TO,	CHAFSR_TO_msg		},
	{	CHAFSR_BERR,	CHAFSR_BERR_msg		},
	/* These two do not update the AFAR. */
	{	CHAFSR_IVC,	CHAFSR_IVC_msg		},
	{	CHAFSR_IVU,	CHAFSR_IVU_msg		},
	{	0,		NULL			},
};
static const char CHPAFSR_DTO_msg[] =
	"System bus unmapped error for prefetch/storequeue-read";
static const char CHPAFSR_DBERR_msg[] =
	"System bus error for prefetch/storequeue-read";
static const char CHPAFSR_THCE_msg[] =
	"Hardware corrected E-cache Tag ECC error";
static const char CHPAFSR_TSCE_msg[] =
	"SW handled correctable E-cache Tag ECC error";
static const char CHPAFSR_TUE_msg[] =
	"Uncorrectable E-cache Tag ECC error";
static const char CHPAFSR_DUE_msg[] =
	"System bus uncorrectable data ECC error due to prefetch/store-fill";
static struct afsr_error_table __cheetah_plus_error_table[] = {
	{	CHAFSR_PERR,	CHAFSR_PERR_msg		},
	{	CHAFSR_IERR,	CHAFSR_IERR_msg		},
	{	CHAFSR_ISAP,	CHAFSR_ISAP_msg		},
	{	CHAFSR_UCU,	CHAFSR_UCU_msg		},
	{	CHAFSR_UCC,	CHAFSR_UCC_msg		},
	{	CHAFSR_UE,	CHAFSR_UE_msg		},
	{	CHAFSR_EDU,	CHAFSR_EDU_msg		},
	{	CHAFSR_EMU,	CHAFSR_EMU_msg		},
	{	CHAFSR_WDU,	CHAFSR_WDU_msg		},
	{	CHAFSR_CPU,	CHAFSR_CPU_msg		},
	{	CHAFSR_CE,	CHAFSR_CE_msg		},
	{	CHAFSR_EDC,	CHAFSR_EDC_msg		},
	{	CHAFSR_EMC,	CHAFSR_EMC_msg		},
	{	CHAFSR_WDC,	CHAFSR_WDC_msg		},
	{	CHAFSR_CPC,	CHAFSR_CPC_msg		},
	{	CHAFSR_TO,	CHAFSR_TO_msg		},
	{	CHAFSR_BERR,	CHAFSR_BERR_msg		},
	{	CHPAFSR_DTO,	CHPAFSR_DTO_msg		},
	{	CHPAFSR_DBERR,	CHPAFSR_DBERR_msg	},
	{	CHPAFSR_THCE,	CHPAFSR_THCE_msg	},
	{	CHPAFSR_TSCE,	CHPAFSR_TSCE_msg	},
	{	CHPAFSR_TUE,	CHPAFSR_TUE_msg		},
	{	CHPAFSR_DUE,	CHPAFSR_DUE_msg		},
	/* These two do not update the AFAR. */
	{	CHAFSR_IVC,	CHAFSR_IVC_msg		},
	{	CHAFSR_IVU,	CHAFSR_IVU_msg		},
	{	0,		NULL			},
};
static const char JPAFSR_JETO_msg[] =
	"System interface protocol error, hw timeout caused";
static const char JPAFSR_SCE_msg[] =
	"Parity error on system snoop results";
static const char JPAFSR_JEIC_msg[] =
	"System interface protocol error, illegal command detected";
static const char JPAFSR_JEIT_msg[] =
	"System interface protocol error, illegal ADTYPE detected";
static const char JPAFSR_OM_msg[] =
	"Out of range memory error has occurred";
static const char JPAFSR_ETP_msg[] =
	"Parity error on L2 cache tag SRAM";
static const char JPAFSR_UMS_msg[] =
	"Error due to unsupported store";
static const char JPAFSR_RUE_msg[] =
	"Uncorrectable ECC error from remote cache/memory";
static const char JPAFSR_RCE_msg[] =
	"Correctable ECC error from remote cache/memory";
static const char JPAFSR_BP_msg[] =
	"JBUS parity error on returned read data";
static const char JPAFSR_WBP_msg[] =
	"JBUS parity error on data for writeback or block store";
static const char JPAFSR_FRC_msg[] =
	"Foreign read to DRAM incurring correctable ECC error";
static const char JPAFSR_FRU_msg[] =
	"Foreign read to DRAM incurring uncorrectable ECC error";
static struct afsr_error_table __jalapeno_error_table[] = {
	{	JPAFSR_JETO,	JPAFSR_JETO_msg		},
	{	JPAFSR_SCE,	JPAFSR_SCE_msg		},
	{	JPAFSR_JEIC,	JPAFSR_JEIC_msg		},
	{	JPAFSR_JEIT,	JPAFSR_JEIT_msg		},
	{	CHAFSR_PERR,	CHAFSR_PERR_msg		},
	{	CHAFSR_IERR,	CHAFSR_IERR_msg		},
	{	CHAFSR_ISAP,	CHAFSR_ISAP_msg		},
	{	CHAFSR_UCU,	CHAFSR_UCU_msg		},
	{	CHAFSR_UCC,	CHAFSR_UCC_msg		},
	{	CHAFSR_UE,	CHAFSR_UE_msg		},
	{	CHAFSR_EDU,	CHAFSR_EDU_msg		},
	{	JPAFSR_OM,	JPAFSR_OM_msg		},
	{	CHAFSR_WDU,	CHAFSR_WDU_msg		},
	{	CHAFSR_CPU,	CHAFSR_CPU_msg		},
	{	CHAFSR_CE,	CHAFSR_CE_msg		},
	{	CHAFSR_EDC,	CHAFSR_EDC_msg		},
	{	JPAFSR_ETP,	JPAFSR_ETP_msg		},
	{	CHAFSR_WDC,	CHAFSR_WDC_msg		},
	{	CHAFSR_CPC,	CHAFSR_CPC_msg		},
	{	CHAFSR_TO,	CHAFSR_TO_msg		},
	{	CHAFSR_BERR,	CHAFSR_BERR_msg		},
	{	JPAFSR_UMS,	JPAFSR_UMS_msg		},
	{	JPAFSR_RUE,	JPAFSR_RUE_msg		},
	{	JPAFSR_RCE,	JPAFSR_RCE_msg		},
	{	JPAFSR_BP,	JPAFSR_BP_msg		},
	{	JPAFSR_WBP,	JPAFSR_WBP_msg		},
	{	JPAFSR_FRC,	JPAFSR_FRC_msg		},
	{	JPAFSR_FRU,	JPAFSR_FRU_msg		},
	/* These two do not update the AFAR. */
	{	CHAFSR_IVU,	CHAFSR_IVU_msg		},
	{	0,		NULL			},
};
static struct afsr_error_table *cheetah_error_table;
static unsigned long cheetah_afsr_errors;

/* This is allocated at boot time based upon the largest hardware
 * cpu ID in the system.  We allocate two entries per cpu, one for
 * TL==0 logging and one for TL >= 1 logging.
 */
struct cheetah_err_info *cheetah_error_log;

static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
{
	struct cheetah_err_info *p;
	int cpu = smp_processor_id();

	if (!cheetah_error_log)
		return NULL;

	p = cheetah_error_log + (cpu * 2);
	if ((afsr & CHAFSR_TL1) != 0UL)
		p++;

	return p;
}

extern unsigned int tl0_icpe[], tl1_icpe[];
extern unsigned int tl0_dcpe[], tl1_dcpe[];
extern unsigned int tl0_fecc[], tl1_fecc[];
extern unsigned int tl0_cee[], tl1_cee[];
extern unsigned int tl0_iae[], tl1_iae[];
extern unsigned int tl0_dae[], tl1_dae[];
extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];

void __init cheetah_ecache_flush_init(void)
{
	unsigned long largest_size, smallest_linesize, order, ver;
	int node, i, instance;

	/* Scan all cpu device tree nodes, note two values:
	 * 1) largest E-cache size
	 * 2) smallest E-cache line size
	 */
	largest_size = 0UL;
	smallest_linesize = ~0UL;

	instance = 0;
	while (!cpu_find_by_instance(instance, &node, NULL)) {
		unsigned long val;

		val = prom_getintdefault(node, "ecache-size",
					 (2 * 1024 * 1024));
		if (val > largest_size)
			largest_size = val;
		val = prom_getintdefault(node, "ecache-line-size", 64);
		if (val < smallest_linesize)
			smallest_linesize = val;
		instance++;
	}

	if (largest_size == 0UL || smallest_linesize == ~0UL) {
		prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
			    "parameters.\n");
		prom_halt();
	}

	ecache_flush_size = (2 * largest_size);
	ecache_flush_linesize = smallest_linesize;

	/* Discover a physically contiguous chunk of physical
	 * memory in 'sp_banks' of size ecache_flush_size calculated
	 * above.  Store the physical base of this area at
	 * ecache_flush_physbase.
	 */
	for (node = 0; ; node++) {
		if (sp_banks[node].num_bytes == 0)
			break;
		if (sp_banks[node].num_bytes >= ecache_flush_size) {
			ecache_flush_physbase = sp_banks[node].base_addr;
			break;
		}
	}

	/* Note: Zero would be a valid value of ecache_flush_physbase so
	 * don't use that as the success test. :-)
	 */
	if (sp_banks[node].num_bytes == 0) {
		prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
			    "contiguous physical memory.\n", ecache_flush_size);
		prom_halt();
	}

	/* Now allocate error trap reporting scoreboard. */
	node = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
	for (order = 0; order < MAX_ORDER; order++) {
		if ((PAGE_SIZE << order) >= node)
			break;
	}
	cheetah_error_log = (struct cheetah_err_info *)
		__get_free_pages(GFP_KERNEL, order);
	if (!cheetah_error_log) {
		prom_printf("cheetah_ecache_flush_init: Failed to allocate "
			    "error logging scoreboard (%d bytes).\n", node);
		prom_halt();
	}
	memset(cheetah_error_log, 0, PAGE_SIZE << order);

	/* Mark all AFSRs as invalid so that the trap handler will
	 * log new new information there.
	 */
	for (i = 0; i < 2 * NR_CPUS; i++)
		cheetah_error_log[i].afsr = CHAFSR_INVALID;

	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
	if ((ver >> 32) == 0x003e0016) {
		cheetah_error_table = &__jalapeno_error_table[0];
		cheetah_afsr_errors = JPAFSR_ERRORS;
	} else if ((ver >> 32) == 0x003e0015) {
		cheetah_error_table = &__cheetah_plus_error_table[0];
		cheetah_afsr_errors = CHPAFSR_ERRORS;
	} else {
		cheetah_error_table = &__cheetah_error_table[0];
		cheetah_afsr_errors = CHAFSR_ERRORS;
	}

	/* Now patch trap tables. */
	memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
	memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
	memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
	memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
	memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
	memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
	memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
	memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
	if (tlb_type == cheetah_plus) {
		memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
		memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
		memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
		memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
	}
	flushi(PAGE_OFFSET);
}

static void cheetah_flush_ecache(void)
{
	unsigned long flush_base = ecache_flush_physbase;
	unsigned long flush_linesize = ecache_flush_linesize;
	unsigned long flush_size = ecache_flush_size;

	__asm__ __volatile__("1: subcc	%0, %4, %0\n\t"
			     "   bne,pt	%%xcc, 1b\n\t"
			     "    ldxa	[%2 + %0] %3, %%g0\n\t"
			     : "=&r" (flush_size)
			     : "0" (flush_size), "r" (flush_base),
			       "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
}

static void cheetah_flush_ecache_line(unsigned long physaddr)
{
	unsigned long alias;

	physaddr &= ~(8UL - 1UL);
	physaddr = (ecache_flush_physbase +
		    (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
	alias = physaddr + (ecache_flush_size >> 1UL);
	__asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
			     "ldxa [%1] %2, %%g0\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (physaddr), "r" (alias),
			       "i" (ASI_PHYS_USE_EC));
}

#ifdef CONFIG_SMP
unsigned long __init cheetah_tune_scheduling(void)
{
	unsigned long tick1, tick2, raw;
	unsigned long flush_base = ecache_flush_physbase;
	unsigned long flush_linesize = ecache_flush_linesize;
	unsigned long flush_size = ecache_flush_size;

	/* Run through the whole cache to guarantee the timed loop
	 * is really displacing cache lines.
	 */
	__asm__ __volatile__("1: subcc	%0, %4, %0\n\t"
			     "   bne,pt	%%xcc, 1b\n\t"
			     "    ldxa	[%2 + %0] %3, %%g0\n\t"
			     : "=&r" (flush_size)
			     : "0" (flush_size), "r" (flush_base),
			       "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));

	/* The flush area is 2 X Ecache-size, so cut this in half for
	 * the timed loop.
	 */
	flush_base = ecache_flush_physbase;
	flush_linesize = ecache_flush_linesize;
	flush_size = ecache_flush_size >> 1;

	tick1 = tick_ops->get_tick();

	__asm__ __volatile__("1: subcc	%0, %4, %0\n\t"
			     "   bne,pt	%%xcc, 1b\n\t"
			     "    ldxa	[%2 + %0] %3, %%g0\n\t"
			     : "=&r" (flush_size)
			     : "0" (flush_size), "r" (flush_base),
			       "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));

	tick2 = tick_ops->get_tick();

	raw = (tick2 - tick1);

	return (raw - (raw >> 2));
}
#endif

/* Unfortunately, the diagnostic access to the I-cache tags we need to
 * use to clear the thing interferes with I-cache coherency transactions.
 *
 * So we must only flush the I-cache when it is disabled.
 */
static void __cheetah_flush_icache(void)
{
	unsigned long i;

	/* Clear the valid bits in all the tags. */
	for (i = 0; i < (1 << 15); i += (1 << 5)) {
		__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
				     "membar #Sync"
				     : /* no outputs */
				     : "r" (i | (2 << 3)), "i" (ASI_IC_TAG));
	}