sincos.twr

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise e:\dds(9854)_test(sin_cos)\sincos.ise -intstyle
ise -e 3 -l 3 -s 5 -xml sincos sincos.ncd -o sincos.twr sincos.pcf


Design file:              sincos.ncd
Physical constraint file: sincos.pcf
Device,speed:             xc2s200,-5 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
a<0>        |    7.703(R)|clk_BUFGP         |   0.000|
a<1>        |    7.703(R)|clk_BUFGP         |   0.000|
a<2>        |    7.700(R)|clk_BUFGP         |   0.000|
a<3>        |    7.700(R)|clk_BUFGP         |   0.000|
a<4>        |    7.703(R)|clk_BUFGP         |   0.000|
a<5>        |    7.703(R)|clk_BUFGP         |   0.000|
d<0>        |    7.700(R)|clk_BUFGP         |   0.000|
d<2>        |    7.703(R)|clk_BUFGP         |   0.000|
d<3>        |    7.700(R)|clk_BUFGP         |   0.000|
d<4>        |    7.700(R)|clk_BUFGP         |   0.000|
d<6>        |    7.703(R)|clk_BUFGP         |   0.000|
d<7>        |    7.700(R)|clk_BUFGP         |   0.000|
io_ud       |    7.747(R)|clk_BUFGP         |   0.000|
mst_rst     |    7.703(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    8.248|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
clk            |wrb            |   10.148|
---------------+---------------+---------+

Analysis completed Fri Aug 05 09:18:09 2011
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Peak Memory Usage: 66 MB