sincos.rpt

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cpldfit:  version H.38                              Xilinx Inc.
                                  Fitter Report
Design Name: sincos                              Date: 10-17-2009,  8:55AM
Device Used: XC95144XL-5-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
43 /144 ( 30%) 150 /720  ( 21%) 57 /432 ( 13%)   42 /144 ( 29%) 18 /117 ( 15%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           9/18       15/54       19/90       9/15
FB2          18/18*      12/54       61/90       7/15
FB3          10/18       12/54       43/90       1/15
FB4           4/18       11/54       22/90       0/15
FB5           2/18        7/54        5/90       0/14
FB6           0/18        0/54        0/90       0/13
FB7           0/18        0/54        0/90       0/15
FB8           0/18        0/54        0/90       0/15
             -----       -----       -----      -----    
             43/144      57/432     150/720     17/117

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :    16     109
Output        :   17          17    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     1       4
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     18          18

** Power Data **

There are 43 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 17 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
d<0>                2     2     FB1_1   23   I/O     O       STD  FAST RESET
d<3>                2     2     FB1_2   16   I/O     O       STD  FAST RESET
a<2>                2     2     FB1_3   17   I/O     O       STD  FAST RESET
mst_rst             3     7     FB1_4   25   I/O     O       STD  FAST RESET
d<5>                2     2     FB1_5   19   I/O     O       STD  FAST RESET
a<4>                2     2     FB1_8   21   I/O     O       STD  FAST RESET
d<7>                2     2     FB1_9   22   I/O     O       STD  FAST RESET
d<4>                2     2     FB1_10  31   I/O     O       STD  FAST RESET
d<6>                2     2     FB1_15  28   I/O     O       STD  FAST RESET
a<1>                2     2     FB2_9   6    GTS/I/O O       STD  FAST RESET
io_ud               2     7     FB2_10  7    I/O     O       STD  FAST RESET
a<3>                2     2     FB2_11  9    I/O     O       STD  FAST RESET
a<5>                2     2     FB2_13  12   I/O     O       STD  FAST RESET
wrb                 1     1     FB2_15  13   I/O     O       STD  FAST 
d<1>                2     2     FB2_16  14   I/O     O       STD  FAST RESET
a<0>                2     2     FB2_17  15   I/O     O       STD  FAST RESET
d<2>                2     2     FB3_8   38   GCK/I/O O       STD  FAST RESET

** 26 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
count<4>            2     5     FB2_1   STD  RESET
count<3>            2     4     FB2_2   STD  RESET
count<1>            2     2     FB2_3   STD  RESET
count<0>            2     7     FB2_4   STD  RESET
count<5>            3     7     FB2_5   STD  RESET
count<2>            3     7     FB2_6   STD  RESET
address_tmp<5>      5     8     FB2_7   STD  RESET
address_tmp<3>      5     8     FB2_8   STD  RESET
data_tmp<1>         7     8     FB2_12  STD  RESET
address_tmp<1>      8     8     FB2_14  STD  RESET
address_tmp<0>      9     8     FB2_18  STD  RESET
data_tmp<2>         8     8     FB3_1   STD  RESET
dount<4>            1     1     FB3_10  STD  RESET
dount<3>            1     1     FB3_11  STD  RESET
dount<2>            1     1     FB3_12  STD  RESET
address_tmp<2>      6     8     FB3_13  STD  RESET
data_tmp<6>         7     8     FB3_14  STD  RESET
dount<5>            1     1     FB3_15  STD  RESET
data_tmp<4>         8     8     FB3_16  STD  RESET
data_tmp<3>         8     8     FB3_18  STD  RESET
data_tmp<5>         5     8     FB4_15  STD  RESET
data_tmp<0>         5     7     FB4_16  STD  RESET
data_tmp<7>         6     8     FB4_17  STD  RESET
address_tmp<4>      6     8     FB4_18  STD  RESET
dount<1>            2     7     FB5_17  STD  RESET
dount<0>            3     7     FB5_18  STD  RESET

** 1 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
clk                 FB4_5   128  I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               15/39
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
d<0>                  2       0     0   3     FB1_1   23    I/O     O
d<3>                  2       0     0   3     FB1_2   16    I/O     O
a<2>                  2       0     0   3     FB1_3   17    I/O     O
mst_rst               3       0     0   2     FB1_4   25    I/O     O
d<5>                  2       0     0   3     FB1_5   19    I/O     O
(unused)              0       0     0   5     FB1_6   20    I/O     
(unused)              0       0     0   5     FB1_7         (b)     
a<4>                  2       0     0   3     FB1_8   21    I/O     O
d<7>                  2       0     0   3     FB1_9   22    I/O     O
d<4>                  2       0     0   3     FB1_10  31    I/O     O
(unused)              0       0     0   5     FB1_11  24    I/O     
(unused)              0       0     0   5     FB1_12  26    I/O     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  27    I/O     
d<6>                  2       0     0   3     FB1_15  28    I/O     O
(unused)              0       0     0   5     FB1_16  35    I/O     
(unused)              0       0     0   5     FB1_17  30    GCK/I/O 
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: address_tmp<2>     6: data_tmp<4>       11: dount<1> 
  2: address_tmp<4>     7: data_tmp<5>       12: dount<2> 
  3: clk                8: data_tmp<6>       13: dount<3> 
  4: data_tmp<0>        9: data_tmp<7>       14: dount<4> 
  5: data_tmp<3>       10: dount<0>          15: dount<5> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
d<0>                 ..XX.................................... 2
d<3>                 ..X.X................................... 2
a<2>                 X.X..................................... 2
mst_rst              ..X......XXXXXX......................... 7
d<5>                 ..X...X................................. 2
a<4>                 .XX..................................... 2
d<7>                 ..X.....X............................... 2
d<4>                 ..X..X.................................. 2
d<6>                 ..X....X................................ 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               12/42
Number of signals used by logic mapping into function block:  12
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
count<4>              2       0   /\1   2     FB2_1   142   I/O     (b)
count<3>              2       0     0   3     FB2_2   143   GSR/I/O (b)
count<1>              2       0     0   3     FB2_3         (b)     (b)
count<0>              2       0     0   3     FB2_4   4     I/O     (b)
count<5>              3       0     0   2     FB2_5   2     GTS/I/O (b)
count<2>              3       0     0   2     FB2_6   3     GTS/I/O (b)
address_tmp<5>        5       0     0   0     FB2_7         (b)     (b)
address_tmp<3>        5       0     0   0     FB2_8   5     GTS/I/O (b)
a<1>                  2       0     0   3     FB2_9   6     GTS/I/O O
io_ud                 2       0     0   3     FB2_10  7     I/O     O
a<3>                  2       0   \/1   2     FB2_11  9     I/O     O
data_tmp<1>           7       2<-   0   0     FB2_12  10    I/O     (b)
a<5>                  2       0   /\1   2     FB2_13  12    I/O     O
address_tmp<1>        8       3<-   0   0     FB2_14  11    I/O     (b)
wrb                   1       0   /\3   1     FB2_15  13    I/O     O
d<1>                  2       0     0   3     FB2_16  14    I/O     O
a<0>                  2       0   \/3   0     FB2_17  15    I/O     O
address_tmp<0>        9       4<-   0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: address_tmp<0>     5: clk                9: count<3> 
  2: address_tmp<1>     6: count<0>          10: count<4> 
  3: address_tmp<3>     7: count<1>          11: count<5> 
  4: address_tmp<5>     8: count<2>          12: data_tmp<1> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
count<4>             ....XXXXX............................... 5
count<3>             ....XXXX................................ 4
count<1>             ....XX.................................. 2
count<0>             ....XXXXXXX............................. 7
count<5>             ....XXXXXXX............................. 7
count<2>             ....XXXXXXX............................. 7
address_tmp<5>       ...XXXXXXXX............................. 8
address_tmp<3>       ..X.XXXXXXX............................. 8
a<1>                 .X..X................................... 2
io_ud                ....XXXXXXX............................. 7
a<3>                 ..X.X................................... 2
data_tmp<1>          ....XXXXXXXX............................ 8
a<5>                 ...XX................................... 2
address_tmp<1>       .X..XXXXXXX............................. 8
wrb                  ....X................................... 1
d<1>                 ....X......X............................ 2
a<0>                 X...X................................... 2
address_tmp<0>       X...XXXXXXX............................. 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               12/42
Number of signals used by logic mapping into function block:  12
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
data_tmp<2>           8       3<-   0   0     FB3_1   39    I/O     (b)
(unused)              0       0   /\3   2     FB3_2   32    GCK/I/O (b)
(unused)              0       0     0   5     FB3_3   41    I/O     
(unused)              0       0     0   5     FB3_4   44    I/O     
(unused)              0       0     0   5     FB3_5   33    I/O     
(unused)              0       0     0   5     FB3_6   34    I/O     
(unused)              0       0     0   5     FB3_7   46    I/O     
d<2>                  2       0     0   3     FB3_8   38    GCK/I/O O
(unused)              0       0     0   5     FB3_9   40    I/O     
dount<4>              1       0     0   4     FB3_10  48    I/O     (b)
dount<3>              1       0     0   4     FB3_11  43    I/O     (b)
dount<2>              1       0   \/3   1     FB3_12  45    I/O     (b)
address_tmp<2>        6       3<- \/2   0     FB3_13        (b)     (b)
data_tmp<6>           7       2<-   0   0     FB3_14  49    I/O     (b)
dount<5>              1       0   \/3   1     FB3_15  50    I/O     (b)
data_tmp<4>           8       3<-   0   0     FB3_16        (b)     (b)
(unused)              0       0   \/3   2     FB3_17  51    I/O     (b)