sincos_timesim.vhd

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-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.42
--  \   \         Application: netgen
--  /   /         Filename: sincos_timesim.vhd
-- /___/   /\     Timestamp: Wed May 06 10:53:23 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim sincos.nga sincos_timesim.vhd 
-- Device	: XC95144XL-5-TQ144 (Speed File: Version 3.0)
-- Input file	: sincos.nga
-- Output file	: sincos_timesim.vhd
-- # of Entities	: 1
-- Design Name	: sincos.nga
-- Xilinx	: C:/Xilinx
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity sincos is
  port (
    clk : in STD_LOGIC := 'X'; 
    io_ud : out STD_LOGIC; 
    mst_rst : out STD_LOGIC; 
    wrb : out STD_LOGIC; 
    a : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    d : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end sincos;

architecture Structure of sincos is
  signal clk_IBUF : STD_LOGIC; 
  signal a_0 : STD_LOGIC; 
  signal a_1 : STD_LOGIC; 
  signal a_2 : STD_LOGIC; 
  signal a_3 : STD_LOGIC; 
  signal a_4 : STD_LOGIC; 
  signal a_5 : STD_LOGIC; 
  signal d_0 : STD_LOGIC; 
  signal d_1 : STD_LOGIC; 
  signal d_2 : STD_LOGIC; 
  signal d_3 : STD_LOGIC; 
  signal d_4 : STD_LOGIC; 
  signal d_5 : STD_LOGIC; 
  signal d_6 : STD_LOGIC; 
  signal d_7 : STD_LOGIC; 
  signal io_ud_OBUF : STD_LOGIC; 
  signal mst_rst_OBUF : STD_LOGIC; 
  signal wrb_OBUF : STD_LOGIC; 
  signal count_2_Q : STD_LOGIC; 
  signal count_2_D : STD_LOGIC; 
  signal count_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_2_CLKF : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal count_2_D1 : STD_LOGIC; 
  signal count_2_D2 : STD_LOGIC; 
  signal count_2_D2_PT_0 : STD_LOGIC; 
  signal count_2_D2_PT_1 : STD_LOGIC; 
  signal count_3_Q : STD_LOGIC; 
  signal count_3_D : STD_LOGIC; 
  signal count_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_3_CLKF : STD_LOGIC; 
  signal count_3_D1 : STD_LOGIC; 
  signal count_3_D2 : STD_LOGIC; 
  signal count_1_Q : STD_LOGIC; 
  signal count_1_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_1_EXP : STD_LOGIC; 
  signal count_1_D : STD_LOGIC; 
  signal count_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_1_CLKF : STD_LOGIC; 
  signal count_1_D1 : STD_LOGIC; 
  signal count_1_D2 : STD_LOGIC; 
  signal count_0_Q : STD_LOGIC; 
  signal count_0_D : STD_LOGIC; 
  signal count_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_0_CLKF : STD_LOGIC; 
  signal count_0_D1 : STD_LOGIC; 
  signal count_0_D2 : STD_LOGIC; 
  signal count_4_Q : STD_LOGIC; 
  signal count_4_D : STD_LOGIC; 
  signal count_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_4_CLKF : STD_LOGIC; 
  signal count_4_D1 : STD_LOGIC; 
  signal count_4_D2 : STD_LOGIC; 
  signal count_5_Q : STD_LOGIC; 
  signal count_5_D : STD_LOGIC; 
  signal count_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_5_CLKF : STD_LOGIC; 
  signal count_5_D1 : STD_LOGIC; 
  signal count_5_D2 : STD_LOGIC; 
  signal count_5_D2_PT_0 : STD_LOGIC; 
  signal count_5_D2_PT_1 : STD_LOGIC; 
  signal dount_0_Q : STD_LOGIC; 
  signal dount_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal dount_0_EXP : STD_LOGIC; 
  signal dount_0_D : STD_LOGIC; 
  signal dount_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal dount_0_CLKF : STD_LOGIC; 
  signal dount_0_D1 : STD_LOGIC; 
  signal dount_0_D2 : STD_LOGIC; 
  signal dount_0_EXP_PT_0 : STD_LOGIC; 
  signal dount_0_EXP_PT_1 : STD_LOGIC; 
  signal dount_0_EXP_PT_2 : STD_LOGIC; 
  signal dount_0_EXP_PT_3 : STD_LOGIC; 
  signal count_6_Q : STD_LOGIC; 
  signal count_6_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_6_EXP : STD_LOGIC; 
  signal count_6_D : STD_LOGIC; 
  signal count_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_6_CLKF : STD_LOGIC; 
  signal count_6_D1 : STD_LOGIC; 
  signal count_6_D2 : STD_LOGIC; 
  signal dount_1_Q : STD_LOGIC; 
  signal dount_1_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal dount_1_EXP : STD_LOGIC; 
  signal dount_1_D : STD_LOGIC; 
  signal dount_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal dount_1_CLKF : STD_LOGIC; 
  signal dount_1_D1 : STD_LOGIC; 
  signal dount_1_D2 : STD_LOGIC; 
  signal dount_1_EXP_PT_0 : STD_LOGIC; 
  signal dount_1_EXP_PT_1 : STD_LOGIC; 
  signal dount_2_Q : STD_LOGIC; 
  signal dount_2_D : STD_LOGIC; 
  signal dount_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal dount_2_CLKF : STD_LOGIC; 
  signal dount_2_D1 : STD_LOGIC; 
  signal dount_2_D2 : STD_LOGIC; 
  signal dount_3_Q : STD_LOGIC; 
  signal dount_3_D : STD_LOGIC; 
  signal dount_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal dount_3_CLKF : STD_LOGIC; 
  signal dount_3_D1 : STD_LOGIC; 
  signal dount_3_D2 : STD_LOGIC; 
  signal dount_4_Q : STD_LOGIC; 
  signal dount_4_D : STD_LOGIC; 
  signal dount_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal dount_4_CLKF : STD_LOGIC; 
  signal dount_4_D1 : STD_LOGIC; 
  signal dount_4_D2 : STD_LOGIC; 
  signal dount_5_Q : STD_LOGIC; 
  signal dount_5_D : STD_LOGIC; 
  signal dount_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal dount_5_CLKF : STD_LOGIC; 
  signal dount_5_D1 : STD_LOGIC; 
  signal dount_5_D2 : STD_LOGIC; 
  signal dount_6_Q : STD_LOGIC; 
  signal dount_6_D : STD_LOGIC; 
  signal dount_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal dount_6_CLKF : STD_LOGIC; 
  signal dount_6_D1 : STD_LOGIC; 
  signal dount_6_D2 : STD_LOGIC; 
  signal address_tmp_0_Q : STD_LOGIC; 
  signal address_tmp_0_D : STD_LOGIC; 
  signal address_tmp_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal address_tmp_0_CLKF : STD_LOGIC; 
  signal address_tmp_0_D1 : STD_LOGIC; 
  signal address_tmp_0_D2 : STD_LOGIC; 
  signal a_3_EXP : STD_LOGIC; 
  signal address_tmp_0_D2_PT_0 : STD_LOGIC; 
  signal address_tmp_0_D2_PT_1 : STD_LOGIC; 
  signal address_tmp_0_D2_PT_2 : STD_LOGIC; 
  signal address_tmp_0_D2_PT_3 : STD_LOGIC; 
  signal address_tmp_0_D2_PT_4 : STD_LOGIC; 
  signal address_tmp_1_Q : STD_LOGIC; 
  signal address_tmp_1_D : STD_LOGIC; 
  signal address_tmp_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal address_tmp_1_CLKF : STD_LOGIC; 
  signal address_tmp_1_D1 : STD_LOGIC; 
  signal address_tmp_1_D2 : STD_LOGIC; 
  signal a_5_EXP : STD_LOGIC; 
  signal address_tmp_1_D2_PT_0 : STD_LOGIC; 
  signal address_tmp_1_D2_PT_1 : STD_LOGIC; 
  signal address_tmp_1_D2_PT_2 : STD_LOGIC; 
  signal address_tmp_1_D2_PT_3 : STD_LOGIC; 
  signal address_tmp_1_D2_PT_4 : STD_LOGIC; 
  signal address_tmp_2_Q : STD_LOGIC; 
  signal address_tmp_2_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal address_tmp_2_EXP : STD_LOGIC; 
  signal address_tmp_2_D : STD_LOGIC; 
  signal address_tmp_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal address_tmp_2_CLKF : STD_LOGIC; 
  signal address_tmp_2_D1 : STD_LOGIC; 
  signal address_tmp_2_D2 : STD_LOGIC; 
  signal address_tmp_2_D2_PT_0 : STD_LOGIC; 
  signal address_tmp_2_D2_PT_1 : STD_LOGIC; 
  signal address_tmp_2_D2_PT_2 : STD_LOGIC; 
  signal address_tmp_2_D2_PT_3 : STD_LOGIC; 
  signal address_tmp_3_Q : STD_LOGIC; 
  signal address_tmp_3_D : STD_LOGIC; 
  signal address_tmp_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal address_tmp_3_CLKF : STD_LOGIC; 
  signal address_tmp_3_D1 : STD_LOGIC; 
  signal address_tmp_3_D2 : STD_LOGIC; 
  signal address_tmp_3_D2_PT_0 : STD_LOGIC; 
  signal address_tmp_3_D2_PT_1 : STD_LOGIC; 
  signal address_tmp_3_D2_PT_2 : STD_LOGIC; 
  signal address_tmp_3_D2_PT_3 : STD_LOGIC; 
  signal address_tmp_4_Q : STD_LOGIC; 
  signal address_tmp_4_D : STD_LOGIC; 
  signal address_tmp_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal address_tmp_4_CLKF : STD_LOGIC; 
  signal address_tmp_4_D1 : STD_LOGIC; 
  signal address_tmp_4_D2 : STD_LOGIC; 
  signal address_tmp_4_D2_PT_0 : STD_LOGIC; 
  signal address_tmp_4_D2_PT_1 : STD_LOGIC; 
  signal address_tmp_4_D2_PT_2 : STD_LOGIC; 
  signal address_tmp_4_D2_PT_3 : STD_LOGIC; 
  signal address_tmp_4_D2_PT_4 : STD_LOGIC; 
  signal address_tmp_5_Q : STD_LOGIC; 
  signal address_tmp_5_D : STD_LOGIC; 
  signal address_tmp_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal address_tmp_5_CLKF : STD_LOGIC; 
  signal address_tmp_5_D1 : STD_LOGIC; 
  signal address_tmp_5_D2 : STD_LOGIC; 
  signal address_tmp_5_D2_PT_0 : STD_LOGIC; 
  signal address_tmp_5_D2_PT_1 : STD_LOGIC; 
  signal address_tmp_5_D2_PT_2 : STD_LOGIC; 
  signal address_tmp_5_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_0_Q : STD_LOGIC; 
  signal data_tmp_0_D : STD_LOGIC; 
  signal data_tmp_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal data_tmp_0_CLKF : STD_LOGIC; 
  signal data_tmp_0_D1 : STD_LOGIC; 
  signal data_tmp_0_D2 : STD_LOGIC; 
  signal data_tmp_4_EXP : STD_LOGIC; 
  signal data_tmp_0_D2_PT_0 : STD_LOGIC; 
  signal data_tmp_0_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_0_D2_PT_2 : STD_LOGIC; 
  signal data_tmp_0_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_0_D2_PT_4 : STD_LOGIC; 
  signal data_tmp_1_Q : STD_LOGIC; 
  signal data_tmp_1_D : STD_LOGIC; 
  signal data_tmp_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal data_tmp_1_CLKF : STD_LOGIC; 
  signal data_tmp_1_D1 : STD_LOGIC; 
  signal data_tmp_1_D2 : STD_LOGIC; 
  signal data_tmp_1_D2_PT_0 : STD_LOGIC; 
  signal a_0_EXP : STD_LOGIC; 
  signal data_tmp_1_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_1_D2_PT_2 : STD_LOGIC; 
  signal data_tmp_1_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_1_D2_PT_4 : STD_LOGIC; 
  signal data_tmp_1_D2_PT_5 : STD_LOGIC; 
  signal data_tmp_2_Q : STD_LOGIC; 
  signal data_tmp_2_D : STD_LOGIC; 
  signal data_tmp_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal data_tmp_2_CLKF : STD_LOGIC; 
  signal data_tmp_2_D1 : STD_LOGIC; 
  signal data_tmp_2_D2 : STD_LOGIC; 
  signal data_tmp_2_D2_PT_0 : STD_LOGIC; 
  signal data_tmp_2_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_2_D2_PT_2 : STD_LOGIC; 
  signal data_tmp_2_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_2_D2_PT_4 : STD_LOGIC; 
  signal data_tmp_3_Q : STD_LOGIC; 
  signal data_tmp_3_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal data_tmp_3_EXP : STD_LOGIC; 
  signal data_tmp_3_D : STD_LOGIC; 
  signal data_tmp_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal data_tmp_3_CLKF : STD_LOGIC; 
  signal data_tmp_3_D1 : STD_LOGIC; 
  signal data_tmp_3_D2 : STD_LOGIC; 
  signal EXP11_EXP : STD_LOGIC; 
  signal data_tmp_3_D2_PT_0 : STD_LOGIC; 
  signal data_tmp_3_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_3_D2_PT_2 : STD_LOGIC; 
  signal data_tmp_3_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_4_Q : STD_LOGIC; 
  signal data_tmp_4_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal data_tmp_4_D : STD_LOGIC; 
  signal data_tmp_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal data_tmp_4_CLKF : STD_LOGIC; 
  signal data_tmp_4_D1 : STD_LOGIC; 
  signal data_tmp_4_D2 : STD_LOGIC; 
  signal EXP12_EXP : STD_LOGIC; 
  signal data_tmp_4_D2_PT_0 : STD_LOGIC; 
  signal data_tmp_4_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_4_D2_PT_2 : STD_LOGIC; 
  signal data_tmp_4_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_5_Q : STD_LOGIC; 
  signal data_tmp_5_D : STD_LOGIC; 
  signal data_tmp_5_CLKF : STD_LOGIC; 
  signal data_tmp_5_D1 : STD_LOGIC; 
  signal data_tmp_5_D2 : STD_LOGIC; 
  signal data_tmp_5_D2_PT_0 : STD_LOGIC; 
  signal data_tmp_5_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_5_D2_PT_2 : STD_LOGIC; 
  signal data_tmp_5_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_5_D2_PT_4 : STD_LOGIC; 
  signal data_tmp_5_D2_PT_5 : STD_LOGIC; 
  signal data_tmp_6_Q : STD_LOGIC; 
  signal data_tmp_6_D : STD_LOGIC; 
  signal data_tmp_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal data_tmp_6_CLKF : STD_LOGIC; 
  signal data_tmp_6_D1 : STD_LOGIC; 
  signal data_tmp_6_D2 : STD_LOGIC; 
  signal data_tmp_7_EXP : STD_LOGIC; 
  signal data_tmp_6_D2_PT_0 : STD_LOGIC; 
  signal data_tmp_6_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_6_D2_PT_2 : STD_LOGIC; 
  signal data_tmp_6_D2_PT_3 : STD_LOGIC; 
  signal data_tmp_6_D2_PT_4 : STD_LOGIC; 
  signal data_tmp_7_Q : STD_LOGIC; 
  signal data_tmp_7_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal data_tmp_7_D : STD_LOGIC; 
  signal data_tmp_7_tsimcreated_xor_Q : STD_LOGIC; 
  signal data_tmp_7_CLKF : STD_LOGIC; 
  signal data_tmp_7_D1 : STD_LOGIC; 
  signal data_tmp_7_D2 : STD_LOGIC; 
  signal EXP10_EXP : STD_LOGIC; 
  signal data_tmp_7_D2_PT_0 : STD_LOGIC; 
  signal data_tmp_7_D2_PT_1 : STD_LOGIC; 
  signal data_tmp_7_EXP_PT_0 : STD_LOGIC; 
  signal data_tmp_7_EXP_PT_1 : STD_LOGIC; 
  signal data_tmp_7_EXP_PT_2 : STD_LOGIC; 
  signal a_0_Q : STD_LOGIC; 
  signal a_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal a_0_D : STD_LOGIC; 
  signal a_0_CLKF : STD_LOGIC; 
  signal a_0_D1 : STD_LOGIC; 
  signal a_0_D2 : STD_LOGIC; 
  signal a_0_EXP_PT_0 : STD_LOGIC; 
  signal a_0_EXP_PT_1 : STD_LOGIC; 
  signal a_0_EXP_PT_2 : STD_LOGIC; 
  signal a_1_Q : STD_LOGIC; 
  signal a_1_D : STD_LOGIC; 
  signal a_1_CLKF : STD_LOGIC; 
  signal a_1_D1 : STD_LOGIC; 
  signal a_1_D2 : STD_LOGIC; 
  signal a_2_Q : STD_LOGIC; 
  signal a_2_D : STD_LOGIC; 
  signal a_2_CLKF : STD_LOGIC; 
  signal a_2_D1 : STD_LOGIC; 
  signal a_2_D2 : STD_LOGIC; 
  signal a_3_Q : STD_LOGIC; 
  signal a_3_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal a_3_D : STD_LOGIC; 
  signal a_3_CLKF : STD_LOGIC; 
  signal a_3_D1 : STD_LOGIC; 
  signal a_3_D2 : STD_LOGIC; 
  signal a_4_Q : STD_LOGIC; 
  signal a_4_D : STD_LOGIC; 
  signal a_4_CLKF : STD_LOGIC; 
  signal a_4_D1 : STD_LOGIC; 
  signal a_4_D2 : STD_LOGIC; 
  signal a_5_Q : STD_LOGIC; 
  signal a_5_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal a_5_D : STD_LOGIC; 
  signal a_5_CLKF : STD_LOGIC; 
  signal a_5_D1 : STD_LOGIC;