📄 graduation.rpt
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FTCPE_div4: FTCPE port map (div(4),div_T(4),clk,'0','0');
div_T(4) <= (div(0) AND div(1) AND div(2) AND div(3));
FTCPE_div5: FTCPE port map (div(5),div_T(5),clk,'0','0');
div_T(5) <= (div(0) AND div(1) AND div(2) AND div(3) AND div(4));
FTCPE_div6: FTCPE port map (div(6),div_T(6),clk,'0','0');
div_T(6) <= (div(0) AND div(1) AND div(2) AND div(3) AND div(4) AND
div(5));
FTCPE_div7: FTCPE port map (div(7),div_T(7),clk,'0','0');
div_T(7) <= (div(0) AND div(1) AND div(2) AND div(3) AND div(4) AND
div(5) AND div(6));
FTCPE_div8: FTCPE port map (div(8),div_T(8),clk,'0','0');
div_T(8) <= (div(0) AND div(1) AND div(2) AND div(3) AND div(4) AND
div(5) AND div(6) AND div(7));
FTCPE_div9: FTCPE port map (div(9),div_T(9),clk,'0','0');
div_T(9) <= (div(0) AND div(1) AND div(2) AND div(3) AND div(4) AND
div(5) AND div(6) AND div(7) AND div(8));
FTCPE_div10: FTCPE port map (div(10),div_T(10),clk,'0','0');
div_T(10) <= (div(0) AND div(1) AND div(2) AND div(3) AND div(4) AND
div(5) AND div(6) AND div(7) AND div(8) AND div(9));
FTCPE_div11: FTCPE port map (div(11),div_T(11),clk,'0','0');
div_T(11) <= (div(0) AND div(10) AND div(1) AND div(2) AND div(3) AND
div(4) AND div(5) AND div(6) AND div(7) AND div(8) AND div(9));
FTCPE_dount0: FTCPE port map (dount(0),dount_T(0),clk,'0','0');
dount_T(0) <= ((NOT dount(2) AND NOT dount(3) AND NOT dount(4) AND NOT dount(5))
OR (NOT dount(0) AND NOT dount(1) AND NOT dount(3) AND NOT dount(4) AND
NOT dount(5)));
FTCPE_dount1: FTCPE port map (dount(1),dount_T(1),clk,'0','0');
dount_T(1) <= (dount(0) AND NOT dount(2) AND NOT dount(3) AND NOT dount(4) AND
NOT dount(5));
FTCPE_dount2: FTCPE port map (dount(2),dount_T(2),clk,'0','0');
dount_T(2) <= (dount(0) AND dount(1) AND NOT dount(2) AND NOT dount(3) AND
NOT dount(4) AND NOT dount(5));
FTCPE_dount3: FTCPE port map (dount(3),'0',clk,'0','0');
FTCPE_dount4: FTCPE port map (dount(4),'0',clk,'0','0');
FTCPE_dount5: FTCPE port map (dount(5),'0',clk,'0','0');
FDCPE_fsk: FDCPE port map (fsk,div(11),clk,'0','0');
FDCPE_io_ud: FDCPE port map (io_ud,io_ud_D,clk,'0','0');
io_ud_D <= (count(2) AND count(1) AND NOT count(3) AND count(4) AND
count(0) AND NOT count(5));
FDCPE_mst_rst: FDCPE port map (mst_rst,dount(1).EXP,clk,'0','0');
FDCPE_output27: FDCPE port map (output2(7),state(19),clk,'0','0');
FTCPE_state0: FTCPE port map (state(0),'1',clk,'0','0');
FTCPE_state1: FTCPE port map (state(1),state(0),clk,'0','0');
FTCPE_state2: FTCPE port map (state(2),state_T(2),clk,'0','0');
state_T(2) <= (state(0) AND state(1));
FTCPE_state3: FTCPE port map (state(3),state_T(3),clk,'0','0');
state_T(3) <= (state(0) AND state(1) AND state(2));
FTCPE_state4: FTCPE port map (state(4),state_T(4),clk,'0','0');
state_T(4) <= (state(0) AND state(1) AND state(2) AND state(3));
FTCPE_state5: FTCPE port map (state(5),state_T(5),clk,'0','0');
state_T(5) <= (state(0) AND state(1) AND state(2) AND state(3) AND
state(4));
FTCPE_state6: FTCPE port map (state(6),state_T(6),clk,'0','0');
state_T(6) <= (state(0) AND state(1) AND state(2) AND state(3) AND
state(4) AND state(5));
FTCPE_state7: FTCPE port map (state(7),state_T(7),clk,'0','0');
state_T(7) <= (state(0) AND state(1) AND state(2) AND state(3) AND
state(4) AND state(5) AND state(6));
FTCPE_state8: FTCPE port map (state(8),state_T(8),clk,'0','0');
state_T(8) <= (state(0) AND state(1) AND state(2) AND state(3) AND
state(4) AND state(5) AND state(6) AND state(7));
FTCPE_state9: FTCPE port map (state(9),state_T(9),clk,'0','0');
state_T(9) <= (state(0) AND state(1) AND state(2) AND state(3) AND
state(4) AND state(5) AND state(6) AND state(7) AND state(8));
FTCPE_state10: FTCPE port map (state(10),state_T(10),clk,'0','0');
state_T(10) <= (state(0) AND state(1) AND state(2) AND state(3) AND
state(4) AND state(5) AND state(6) AND state(7) AND state(8) AND
state(9));
FTCPE_state11: FTCPE port map (state(11),state_T(11),clk,'0','0');
state_T(11) <= (state(0) AND state(10) AND state(1) AND state(2) AND
state(3) AND state(4) AND state(5) AND state(6) AND state(7) AND
state(8) AND state(9));
FTCPE_state12: FTCPE port map (state(12),state_T(12),clk,'0','0');
state_T(12) <= (state(0) AND state(10) AND state(11) AND state(1) AND
state(2) AND state(3) AND state(4) AND state(5) AND state(6) AND
state(7) AND state(8) AND state(9));
FTCPE_state13: FTCPE port map (state(13),state_T(13),clk,'0','0');
state_T(13) <= (state(0) AND state(10) AND state(11) AND state(12) AND
state(1) AND state(2) AND state(3) AND state(4) AND state(5) AND
state(6) AND state(7) AND state(8) AND state(9));
FTCPE_state14: FTCPE port map (state(14),state_T(14),clk,'0','0');
state_T(14) <= (state(0) AND state(10) AND state(11) AND state(12) AND
state(13) AND state(1) AND state(2) AND state(3) AND state(4) AND
state(5) AND state(6) AND state(7) AND state(8) AND state(9));
FTCPE_state15: FTCPE port map (state(15),state_T(15),clk,'0','0');
state_T(15) <= (state(0) AND state(10) AND state(11) AND state(12) AND
state(13) AND state(14) AND state(1) AND state(2) AND state(3) AND
state(4) AND state(5) AND state(6) AND state(7) AND state(8) AND
state(9));
FTCPE_state16: FTCPE port map (state(16),state_T(16),clk,'0','0');
state_T(16) <= (state(0) AND state(10) AND state(11) AND state(12) AND
state(13) AND state(14) AND state(15) AND state(1) AND state(2) AND
state(3) AND state(4) AND state(5) AND state(6) AND state(7) AND
state(8) AND state(9));
FTCPE_state17: FTCPE port map (state(17),state_T(17),clk,'0','0');
state_T(17) <= (state(0) AND state(10) AND state(11) AND state(12) AND
state(13) AND state(14) AND state(15) AND state(16) AND state(1) AND
state(2) AND state(3) AND state(4) AND state(5) AND state(6) AND
state(7) AND state(8) AND state(9));
FTCPE_state18: FTCPE port map (state(18),state_T(18),clk,'0','0');
state_T(18) <= (state(0) AND state(10) AND state(11) AND state(12) AND
state(13) AND state(14) AND state(15) AND state(16) AND state(17) AND
state(1) AND state(2) AND state(3) AND state(4) AND state(5) AND
state(6) AND state(7) AND state(8) AND state(9));
FTCPE_state19: FTCPE port map (state(19),state_T(19),clk,'0','0');
state_T(19) <= (state(0) AND state(10) AND state(11) AND state(12) AND
state(13) AND state(14) AND state(15) AND state(16) AND state(17) AND
state(18) AND state(1) AND state(2) AND state(3) AND state(4) AND
state(5) AND state(6) AND state(7) AND state(8) AND state(9));
wrb <= NOT clk;
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-5-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 KPR 74 KPR
3 mst_rst 75 KPR
4 KPR 76 KPR
5 KPR 77 KPR
6 a<4> 78 KPR
7 d<0> 79 KPR
8 VCC 80 KPR
9 a<5> 81 KPR
10 d<2> 82 KPR
11 KPR 83 KPR
12 a<2> 84 VCC
13 d<4> 85 KPR
14 a<3> 86 KPR
15 d<6> 87 KPR
16 a<0> 88 KPR
17 d<7> 89 GND
18 GND 90 GND
19 a<1> 91 KPR
20 KPR 92 KPR
21 d<5> 93 KPR
22 KPR 94 KPR
23 d<3> 95 KPR
24 KPR 96 KPR
25 d<1> 97 KPR
26 wrb 98 KPR
27 KPR 99 GND
28 KPR 100 KPR
29 GND 101 KPR
30 KPR 102 KPR
31 io_ud 103 KPR
32 fsk 104 KPR
33 KPR 105 KPR
34 KPR 106 KPR
35 KPR 107 KPR
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 KPR
39 KPR 111 KPR
40 KPR 112 KPR
41 KPR 113 KPR
42 VCC 114 GND
43 KPR 115 KPR
44 KPR 116 KPR
45 KPR 117 KPR
46 KPR 118 KPR
47 GND 119 KPR
48 KPR 120 KPR
49 KPR 121 KPR
50 KPR 122 TDO
51 KPR 123 GND
52 KPR 124 KPR
53 KPR 125 KPR
54 KPR 126 KPR
55 VCC 127 VCC
56 KPR 128 clk
57 KPR 129 KPR
58 KPR 130 KPR
59 KPR 131 KPR
60 KPR 132 KPR
61 KPR 133 KPR
62 GND 134 KPR
63 TDI 135 KPR
64 dial<2> 136 KPR
65 TMS 137 KPR
66 dial<1> 138 KPR
67 TCK 139 KPR
68 KPR 140 KPR
69 dial<0> 141 VCC
70 KPR 142 KPR
71 KPR 143 KPR
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-5-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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