graduation.rpt

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

 
cpldfit:  version H.42                              Xilinx Inc.
                                  Fitter Report
Design Name: graduation                          Date:  7- 3-2009,  3:00PM
Device Used: XC95144XL-5-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
78 /144 ( 54%) 436 /720  ( 61%) 139/432 ( 32%)   76 /144 ( 53%) 22 /117 ( 19%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           9/18       17/54       40/90       8/15
FB2          14/18       24/54       64/90       9/15
FB3          18/18*      21/54       36/90       1/15
FB4           9/18       15/54       90/90*      0/15
FB5           6/18       24/54       87/90       0/14
FB6          12/18       23/54       70/90       0/13
FB7          10/18       15/54       49/90       0/15
FB8           0/18        0/54        0/90       0/15
             -----       -----       -----      -----    
             78/144     139/432     436/720     18/117

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    4           4    |  I/O              :    19     109
Output        :   18          18    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     2       4
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     22          22

** Power Data **

There are 78 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 18 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
d<3>                2     2     FB1_1   23   I/O     O       STD  FAST RESET
a<0>                2     2     FB1_2   16   I/O     O       STD  FAST RESET
d<7>                2     2     FB1_3   17   I/O     O       STD  FAST RESET
d<1>                2     2     FB1_4   25   I/O     O       STD  FAST RESET
a<1>                2     2     FB1_5   19   I/O     O       STD  FAST RESET
d<5>                2     2     FB1_8   21   I/O     O       STD  FAST RESET
io_ud               2     7     FB1_10  31   I/O     O       STD  FAST RESET
wrb                 1     1     FB1_12  26   I/O     O       STD  FAST 
mst_rst             3     7     FB2_6   3    GTS/I/O O       STD  FAST RESET
a<4>                2     2     FB2_9   6    GTS/I/O O       STD  FAST RESET
d<0>                2     2     FB2_10  7    I/O     O       STD  FAST RESET
a<5>                2     2     FB2_11  9    I/O     O       STD  FAST RESET
d<2>                2     2     FB2_12  10   I/O     O       STD  FAST RESET
a<2>                2     2     FB2_13  12   I/O     O       STD  FAST RESET
d<4>                2     2     FB2_15  13   I/O     O       STD  FAST RESET
a<3>                2     2     FB2_16  14   I/O     O       STD  FAST RESET
d<6>                2     2     FB2_17  15   I/O     O       STD  FAST RESET
fsk                 2     2     FB3_2   32   GCK/I/O O       STD  FAST RESET

** 60 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
data_tmp<3>         25    12    FB1_16  STD  RESET
address_tmp<3>      20    11    FB2_1   STD  RESET
dount<2>            2     7     FB2_4   STD  RESET
dount<1>            2     6     FB2_5   STD  RESET
address_tmp<4>      18    11    FB2_8   STD  RESET
dount<0>            3     7     FB2_14  STD  RESET
state<9>            2     10    FB3_1   STD  RESET
state<8>            2     9     FB3_3   STD  RESET
state<7>            2     8     FB3_4   STD  RESET
state<6>            2     7     FB3_5   STD  RESET
state<5>            2     6     FB3_6   STD  RESET
state<4>            2     5     FB3_7   STD  RESET
state<3>            2     4     FB3_8   STD  RESET
state<19>           2     20    FB3_9   STD  RESET
state<18>           2     19    FB3_10  STD  RESET
state<17>           2     18    FB3_11  STD  RESET
state<16>           2     17    FB3_12  STD  RESET
state<15>           2     16    FB3_13  STD  RESET
state<14>           2     15    FB3_14  STD  RESET
state<13>           2     14    FB3_15  STD  RESET
state<12>           2     13    FB3_16  STD  RESET
state<11>           2     12    FB3_17  STD  RESET
state<10>           2     11    FB3_18  STD  RESET
count<0>            2     7     FB4_1   STD  RESET
data_tmp<6>         25    13    FB4_3   STD  RESET
count<5>            3     7     FB4_6   STD  RESET
count<3>            3     7     FB4_7   STD  RESET
data_tmp<0>         25    12    FB4_10  STD  RESET
count<4>            2     5     FB4_12  STD  RESET
count<2>            2     3     FB4_13  STD  RESET
data_tmp<4>         26    12    FB4_16  STD  RESET
$OpTx$FX_DC$36      2     2     FB4_18  STD  
data_tmp<2>         23    12    FB5_1   STD  RESET
div<9>              2     10    FB5_3   STD  RESET
count<1>            2     2     FB5_4   STD  RESET
data_tmp<5>         18    12    FB5_6   STD  RESET
data_tmp<7>         20    12    FB5_10  STD  RESET
data_tmp<1>         22    12    FB5_14  STD  RESET
div<8>              2     9     FB6_1   STD  RESET
div<7>              2     8     FB6_2   STD  RESET

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
div<6>              2     7     FB6_3   STD  RESET
div<5>              2     6     FB6_4   STD  RESET
div<4>              2     5     FB6_5   STD  RESET
div<3>              2     4     FB6_6   STD  RESET
div<2>              2     3     FB6_7   STD  RESET
div<1>              2     2     FB6_8   STD  RESET
address_tmp<0>      26    11    FB6_11  STD  RESET
div<11>             2     12    FB6_13  STD  RESET
div<10>             2     11    FB6_14  STD  RESET
address_tmp<1>      24    11    FB6_16  STD  RESET
output2<7>          2     2     FB7_4   STD  RESET
state<1>            2     2     FB7_5   STD  RESET
state<2>            2     3     FB7_6   STD  RESET
div<0>              1     1     FB7_7   STD  RESET
dount<3>            1     1     FB7_8   STD  RESET
dount<4>            1     1     FB7_9   STD  RESET
dount<5>            1     1     FB7_10  STD  RESET
state<0>            1     1     FB7_11  STD  RESET
address_tmp<5>      17    11    FB7_14  STD  RESET
address_tmp<2>      21    11    FB7_18  STD  RESET

** 4 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
clk                 FB4_5   128  I/O     I
dial<1>             FB5_7   66   I/O     I
dial<2>             FB5_15  64   I/O     I
dial<0>             FB5_17  69   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
d<3>                  2       0     0   3     FB1_1   23    I/O     O
a<0>                  2       0     0   3     FB1_2   16    I/O     O
d<7>                  2       0     0   3     FB1_3   17    I/O     O
d<1>                  2       0     0   3     FB1_4   25    I/O     O
a<1>                  2       0     0   3     FB1_5   19    I/O     O
(unused)              0       0     0   5     FB1_6   20    I/O     
(unused)              0       0     0   5     FB1_7         (b)     
d<5>                  2       0     0   3     FB1_8   21    I/O     O
(unused)              0       0     0   5     FB1_9   22    I/O     
io_ud                 2       0     0   3     FB1_10  31    I/O     O
(unused)              0       0     0   5     FB1_11  24    I/O     
wrb                   1       0     0   4     FB1_12  26    I/O     O
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0   \/5   0     FB1_14  27    I/O     (b)
(unused)              0       0   \/5   0     FB1_15  28    I/O     (b)
data_tmp<3>          25      20<-   0   0     FB1_16  35    I/O     (b)
(unused)              0       0   /\5   0     FB1_17  30    GCK/I/O (b)
(unused)              0       0   /\5   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: address_tmp<0>     7: count<3>          13: data_tmp<7> 
  2: address_tmp<1>     8: count<4>          14: dial<0> 
  3: clk                9: count<5>          15: dial<1> 
  4: count<0>          10: data_tmp<1>       16: dial<2> 
  5: count<1>          11: data_tmp<3>       17: output2<7> 
  6: count<2>          12: data_tmp<5>      

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
d<3>                 ..X.......X............................. 2
a<0>                 X.X..................................... 2
d<7>                 ..X.........X........................... 2
d<1>                 ..X......X.............................. 2
a<1>                 .XX..................................... 2
d<5>                 ..X........X............................ 2
io_ud                ..XXXXXXX............................... 7
wrb                  ..X..................................... 1
data_tmp<3>          ..XXXXXXX.X..XXXX....................... 12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               24/30
Number of signals used by logic mapping into function block:  24
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
address_tmp<3>       20      15<-   0   0     FB2_1   142   I/O     (b)
(unused)              0       0   /\5   0     FB2_2   143   GSR/I/O (b)
(unused)              0       0   /\2   3     FB2_3         (b)     (b)
dount<2>              2       0     0   3     FB2_4   4     I/O     (b)
dount<1>              2       0   \/2   1     FB2_5   2     GTS/I/O (b)
mst_rst               3       2<- \/4   0     FB2_6   3     GTS/I/O O
(unused)              0       0   \/5   0     FB2_7         (b)     (b)
address_tmp<4>       18      13<-   0   0     FB2_8   5     GTS/I/O (b)
a<4>                  2       1<- /\4   0     FB2_9   6     GTS/I/O O
d<0>                  2       0   /\1   2     FB2_10  7     I/O     O
a<5>                  2       0     0   3     FB2_11  9     I/O     O
d<2>                  2       0     0   3     FB2_12  10    I/O     O
a<2>                  2       0     0   3     FB2_13  12    I/O     O
dount<0>              3       0     0   2     FB2_14  11    I/O     (b)
d<4>                  2       0     0   3     FB2_15  13    I/O     O
a<3>                  2       0     0   3     FB2_16  14    I/O     O
d<6>                  2       0   \/3   0     FB2_17  15    I/O     O
(unused)              0       0   \/5   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: address_tmp<2>     9: count<3>          17: dial<1> 
  2: address_tmp<3>    10: count<4>          18: dial<2> 
  3: address_tmp<4>    11: count<5>          19: dount<0> 
  4: address_tmp<5>    12: data_tmp<0>       20: dount<1> 
  5: clk               13: data_tmp<2>       21: dount<2> 
  6: count<0>          14: data_tmp<4>       22: dount<3> 
  7: count<1>          15: data_tmp<6>       23: dount<4> 
  8: count<2>          16: dial<0>           24: dount<5> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
address_tmp<3>       .X..XXXXXXX....XXX...................... 11
dount<2>             ....X.............XXXXXX................ 7
dount<1>             ....X.............X.XXXX................ 6
mst_rst              ....X.............XXXXXX................ 7
address_tmp<4>       ..X.XXXXXXX....XXX...................... 11
a<4>                 ..X.X................................... 2
d<0>                 ....X......X............................ 2
a<5>                 ...XX................................... 2
d<2>                 ....X.......X........................... 2
a<2>                 X...X................................... 2
dount<0>             ....X.............XXXXXX................ 7
d<4>                 ....X........X.......................... 2
a<3>                 .X..X................................... 2
d<6>                 ....X.........X......................... 2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin