sincos_timesim.sdf

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

        (ABSOLUTE
          (PORT I0 ( 2900 )( 2900 ))
          (PORT I1 ( 2900 )( 2900 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE dount_1_CLKF_88)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND8")
    (INSTANCE dount_1_EXP_PT_0_89)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3600 )( 3600 ))
          (PORT I1 ( 3600 )( 3600 ))
          (PORT I2 ( 3600 )( 3600 ))
          (PORT I3 ( 3600 )( 3600 ))
          (PORT I4 ( 3600 )( 3600 ))
          (PORT I5 ( 3600 )( 3600 ))
          (PORT I6 ( 3600 )( 3600 ))
          (PORT I7 ( 3600 )( 3600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
          (IOPATH I7 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND8")
    (INSTANCE dount_1_EXP_PT_1_90)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3600 )( 3600 ))
          (PORT I1 ( 3600 )( 3600 ))
          (PORT I2 ( 3600 )( 3600 ))
          (PORT I3 ( 3600 )( 3600 ))
          (PORT I4 ( 3600 )( 3600 ))
          (PORT I5 ( 3600 )( 3600 ))
          (PORT I6 ( 3600 )( 3600 ))
          (PORT I7 ( 3600 )( 3600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
          (IOPATH I7 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE dount_1_EXP_tsimrenamed_net_Q_91)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dount_2_Q_92)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_2_tsimcreated_xor_Q_93)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 1400 )( 1400 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE dount_2_REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 400 )( 400 ))
          (IOPATH SET O ( 6000 )( 6000 ))
          (IOPATH RST O ( 6000 )( 6000 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (negedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (10000))
        (WIDTH (posedge SET) (5000))
        (WIDTH (posedge RST) (5000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_2_D_94)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE dount_2_D2_96)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 2900 )( 2900 ))
          (PORT I1 ( 2900 )( 2900 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE dount_2_CLKF_97)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dount_3_Q_98)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_3_tsimcreated_xor_Q_99)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 1400 )( 1400 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE dount_3_REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 400 )( 400 ))
          (IOPATH SET O ( 6000 )( 6000 ))
          (IOPATH RST O ( 6000 )( 6000 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (negedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (10000))
        (WIDTH (posedge SET) (5000))
        (WIDTH (posedge RST) (5000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_3_D_100)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND3")
    (INSTANCE dount_3_D2_102)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 2900 )( 2900 ))
          (PORT I1 ( 2900 )( 2900 ))
          (PORT I2 ( 2900 )( 2900 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE dount_3_CLKF_103)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dount_4_Q_104)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_4_tsimcreated_xor_Q_105)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 1400 )( 1400 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE dount_4_REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 400 )( 400 ))
          (IOPATH SET O ( 6000 )( 6000 ))
          (IOPATH RST O ( 6000 )( 6000 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (negedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (10000))
        (WIDTH (posedge SET) (5000))
        (WIDTH (posedge RST) (5000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_4_D_106)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND4")
    (INSTANCE dount_4_D2_108)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 2900 )( 2900 ))
          (PORT I1 ( 2900 )( 2900 ))
          (PORT I2 ( 2900 )( 2900 ))
          (PORT I3 ( 2900 )( 2900 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE dount_4_CLKF_109)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dount_5_Q_110)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_5_tsimcreated_xor_Q_111)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 1400 )( 1400 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE dount_5_REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 400 )( 400 ))
          (IOPATH SET O ( 6000 )( 6000 ))
          (IOPATH RST O ( 6000 )( 6000 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (negedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (10000))
        (WIDTH (posedge SET) (5000))
        (WIDTH (posedge RST) (5000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_5_D_112)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND5")
    (INSTANCE dount_5_D2_114)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 2900 )( 2900 ))
          (PORT I1 ( 2900 )( 2900 ))
          (PORT I2 ( 2900 )( 2900 ))
          (PORT I3 ( 2900 )( 2900 ))
          (PORT I4 ( 2900 )( 2900 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE dount_5_CLKF_115)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE dount_6_Q_116)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_6_tsimcreated_xor_Q_117)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 1400 )( 1400 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE dount_6_REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 400 )( 400 ))
          (IOPATH SET O ( 6000 )( 6000 ))
          (IOPATH RST O ( 6000 )( 6000 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (negedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (10000))
        (WIDTH (posedge SET) (5000))
        (WIDTH (posedge RST) (5000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE dount_6_D_118)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND7")
    (INSTANCE dount_6_D2_120)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 2900 )( 2900 ))
          (PORT I1 ( 2900 )( 2900 ))
          (PORT I2 ( 2900 )( 2900 ))
          (PORT I3 ( 2900 )( 2900 ))
          (PORT I4 ( 2900 )( 2900 ))
          (PORT I5 ( 2900 )( 2900 ))
          (PORT I6 ( 2900 )( 2900 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE dount_6_CLKF_121)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE address_tmp_0_Q_122)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE address_tmp_0_tsimcreated_xor_Q_123)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 1400 )( 1400 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE address_tmp_0_REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 400 )( 400 ))
          (IOPATH SET O ( 6000 )( 6000 ))
          (IOPATH RST O ( 6000 )( 6000 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (negedge I) (posedge CLK) (2300)(1400))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (10000))
        (WIDTH (posedge SET) (5000))
        (WIDTH (posedge RST) (5000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE address_tmp_0_D_124)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE address_tmp_0_D2_PT_0_126)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE address_tmp_0_D2_PT_1_127)
      (DELAY