sincos_timesim.vhd

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    );
  dount_2_tsimcreated_xor_Q_93 : X_XOR2
    port map (
      I0 => dount_2_D,
      I1 => dount_2_Q,
      O => dount_2_tsimcreated_xor_Q
    );
  dount_2_REG : X_FF
    port map (
      I => dount_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dount_2_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => dount_2_Q
    );
  dount_2_D_94 : X_XOR2
    port map (
      I0 => dount_2_D1,
      I1 => dount_2_D2,
      O => dount_2_D
    );
  dount_2_D1_95 : X_ZERO
    port map (
      O => dount_2_D1
    );
  dount_2_D2_96 : X_AND2
    port map (
      I0 => dount(0),
      I1 => dount(1),
      O => dount_2_D2
    );
  dount_2_CLKF_97 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => dount_2_CLKF
    );
  dount_3_Q_98 : X_BUF
    port map (
      I => dount_3_Q,
      O => dount(3)
    );
  dount_3_tsimcreated_xor_Q_99 : X_XOR2
    port map (
      I0 => dount_3_D,
      I1 => dount_3_Q,
      O => dount_3_tsimcreated_xor_Q
    );
  dount_3_REG : X_FF
    port map (
      I => dount_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dount_3_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => dount_3_Q
    );
  dount_3_D_100 : X_XOR2
    port map (
      I0 => dount_3_D1,
      I1 => dount_3_D2,
      O => dount_3_D
    );
  dount_3_D1_101 : X_ZERO
    port map (
      O => dount_3_D1
    );
  dount_3_D2_102 : X_AND3
    port map (
      I0 => dount(0),
      I1 => dount(1),
      I2 => dount(2),
      O => dount_3_D2
    );
  dount_3_CLKF_103 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => dount_3_CLKF
    );
  dount_4_Q_104 : X_BUF
    port map (
      I => dount_4_Q,
      O => dount(4)
    );
  dount_4_tsimcreated_xor_Q_105 : X_XOR2
    port map (
      I0 => dount_4_D,
      I1 => dount_4_Q,
      O => dount_4_tsimcreated_xor_Q
    );
  dount_4_REG : X_FF
    port map (
      I => dount_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dount_4_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => dount_4_Q
    );
  dount_4_D_106 : X_XOR2
    port map (
      I0 => dount_4_D1,
      I1 => dount_4_D2,
      O => dount_4_D
    );
  dount_4_D1_107 : X_ZERO
    port map (
      O => dount_4_D1
    );
  dount_4_D2_108 : X_AND4
    port map (
      I0 => dount(0),
      I1 => dount(1),
      I2 => dount(2),
      I3 => dount(3),
      O => dount_4_D2
    );
  dount_4_CLKF_109 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => dount_4_CLKF
    );
  dount_5_Q_110 : X_BUF
    port map (
      I => dount_5_Q,
      O => dount(5)
    );
  dount_5_tsimcreated_xor_Q_111 : X_XOR2
    port map (
      I0 => dount_5_D,
      I1 => dount_5_Q,
      O => dount_5_tsimcreated_xor_Q
    );
  dount_5_REG : X_FF
    port map (
      I => dount_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dount_5_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => dount_5_Q
    );
  dount_5_D_112 : X_XOR2
    port map (
      I0 => dount_5_D1,
      I1 => dount_5_D2,
      O => dount_5_D
    );
  dount_5_D1_113 : X_ZERO
    port map (
      O => dount_5_D1
    );
  dount_5_D2_114 : X_AND5
    port map (
      I0 => dount(0),
      I1 => dount(1),
      I2 => dount(2),
      I3 => dount(3),
      I4 => dount(4),
      O => dount_5_D2
    );
  dount_5_CLKF_115 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => dount_5_CLKF
    );
  dount_6_Q_116 : X_BUF
    port map (
      I => dount_6_Q,
      O => dount(6)
    );
  dount_6_tsimcreated_xor_Q_117 : X_XOR2
    port map (
      I0 => dount_6_D,
      I1 => dount_6_Q,
      O => dount_6_tsimcreated_xor_Q
    );
  dount_6_REG : X_FF
    port map (
      I => dount_6_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dount_6_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => dount_6_Q
    );
  dount_6_D_118 : X_XOR2
    port map (
      I0 => dount_6_D1,
      I1 => dount_6_D2,
      O => dount_6_D
    );
  dount_6_D1_119 : X_ZERO
    port map (
      O => dount_6_D1
    );
  dount_6_D2_120 : X_AND7
    port map (
      I0 => dount(0),
      I1 => dount(1),
      I2 => dount(2),
      I3 => dount(3),
      I4 => dount(4),
      I5 => dount(5),
      I6 => dount(6),
      O => dount_6_D2
    );
  dount_6_CLKF_121 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => dount_6_CLKF
    );
  address_tmp_0_Q_122 : X_BUF
    port map (
      I => address_tmp_0_Q,
      O => address_tmp(0)
    );
  address_tmp_0_tsimcreated_xor_Q_123 : X_XOR2
    port map (
      I0 => address_tmp_0_D,
      I1 => address_tmp_0_Q,
      O => address_tmp_0_tsimcreated_xor_Q
    );
  address_tmp_0_REG : X_FF
    port map (
      I => address_tmp_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => address_tmp_0_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => address_tmp_0_Q
    );
  address_tmp_0_D_124 : X_XOR2
    port map (
      I0 => address_tmp_0_D1,
      I1 => address_tmp_0_D2,
      O => address_tmp_0_D
    );
  address_tmp_0_D1_125 : X_ZERO
    port map (
      O => address_tmp_0_D1
    );
  address_tmp_0_D2_PT_0_126 : X_AND2
    port map (
      I0 => a_3_EXP,
      I1 => a_3_EXP,
      O => address_tmp_0_D2_PT_0
    );
  address_tmp_0_D2_PT_1_127 : X_AND6
    port map (
      I0 => NlwInverterSignal_address_tmp_0_D2_PT_1_IN0,
      I1 => count(2),
      I2 => NlwInverterSignal_address_tmp_0_D2_PT_1_IN2,
      I3 => NlwInverterSignal_address_tmp_0_D2_PT_1_IN3,
      I4 => NlwInverterSignal_address_tmp_0_D2_PT_1_IN4,
      I5 => address_tmp(0),
      O => address_tmp_0_D2_PT_1
    );
  address_tmp_0_D2_PT_2_128 : X_AND7
    port map (
      I0 => NlwInverterSignal_address_tmp_0_D2_PT_2_IN0,
      I1 => count(0),
      I2 => count(2),
      I3 => NlwInverterSignal_address_tmp_0_D2_PT_2_IN3,
      I4 => NlwInverterSignal_address_tmp_0_D2_PT_2_IN4,
      I5 => NlwInverterSignal_address_tmp_0_D2_PT_2_IN5,
      I6 => NlwInverterSignal_address_tmp_0_D2_PT_2_IN6,
      O => address_tmp_0_D2_PT_2
    );
  address_tmp_0_D2_PT_3_129 : X_AND7
    port map (
      I0 => NlwInverterSignal_address_tmp_0_D2_PT_3_IN0,
      I1 => NlwInverterSignal_address_tmp_0_D2_PT_3_IN1,
      I2 => count(3),
      I3 => NlwInverterSignal_address_tmp_0_D2_PT_3_IN3,
      I4 => NlwInverterSignal_address_tmp_0_D2_PT_3_IN4,
      I5 => NlwInverterSignal_address_tmp_0_D2_PT_3_IN5,
      I6 => address_tmp(0),
      O => address_tmp_0_D2_PT_3
    );
  address_tmp_0_D2_PT_4_130 : X_AND7
    port map (
      I0 => count(0),
      I1 => NlwInverterSignal_address_tmp_0_D2_PT_4_IN1,
      I2 => count(3),
      I3 => NlwInverterSignal_address_tmp_0_D2_PT_4_IN3,
      I4 => NlwInverterSignal_address_tmp_0_D2_PT_4_IN4,
      I5 => NlwInverterSignal_address_tmp_0_D2_PT_4_IN5,
      I6 => NlwInverterSignal_address_tmp_0_D2_PT_4_IN6,
      O => address_tmp_0_D2_PT_4
    );
  address_tmp_0_D2_131 : X_OR5
    port map (
      I0 => address_tmp_0_D2_PT_0,
      I1 => address_tmp_0_D2_PT_1,
      I2 => address_tmp_0_D2_PT_2,
      I3 => address_tmp_0_D2_PT_3,
      I4 => address_tmp_0_D2_PT_4,
      O => address_tmp_0_D2
    );
  address_tmp_0_CLKF_132 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => address_tmp_0_CLKF
    );
  address_tmp_1_Q_133 : X_BUF
    port map (
      I => address_tmp_1_Q,
      O => address_tmp(1)
    );
  address_tmp_1_tsimcreated_xor_Q_134 : X_XOR2
    port map (
      I0 => address_tmp_1_D,
      I1 => address_tmp_1_Q,
      O => address_tmp_1_tsimcreated_xor_Q
    );
  address_tmp_1_REG : X_FF
    port map (
      I => address_tmp_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => address_tmp_1_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => address_tmp_1_Q
    );
  address_tmp_1_D_135 : X_XOR2
    port map (
      I0 => address_tmp_1_D1,
      I1 => address_tmp_1_D2,
      O => address_tmp_1_D
    );
  address_tmp_1_D1_136 : X_ZERO
    port map (
      O => address_tmp_1_D1
    );
  address_tmp_1_D2_PT_0_137 : X_AND2
    port map (
      I0 => a_5_EXP,
      I1 => a_5_EXP,
      O => address_tmp_1_D2_PT_0
    );
  address_tmp_1_D2_PT_1_138 : X_AND7
    port map (
      I0 => count(1),
      I1 => count(2),
      I2 => NlwInverterSignal_address_tmp_1_D2_PT_1_IN2,
      I3 => NlwInverterSignal_address_tmp_1_D2_PT_1_IN3,
      I4 => NlwInverterSignal_address_tmp_1_D2_PT_1_IN4,
      I5 => NlwInverterSignal_address_tmp_1_D2_PT_1_IN5,
      I6 => NlwInverterSignal_address_tmp_1_D2_PT_1_IN6,
      O => address_tmp_1_D2_PT_1
    );
  address_tmp_1_D2_PT_2_139 : X_AND7
    port map (
      I0 => NlwInverterSignal_address_tmp_1_D2_PT_2_IN0,
      I1 => count(2),
      I2 => count(3),
      I3 => NlwInverterSignal_address_tmp_1_D2_PT_2_IN3,
      I4 => NlwInverterSignal_address_tmp_1_D2_PT_2_IN4,
      I5 => NlwInverterSignal_address_tmp_1_D2_PT_2_IN5,
      I6 => NlwInverterSignal_address_tmp_1_D2_PT_2_IN6,
      O => address_tmp_1_D2_PT_2
    );
  address_tmp_1_D2_PT_3_140 : X_AND7
    port map (
      I0 => NlwInverterSignal_address_tmp_1_D2_PT_3_IN0,
      I1 => count(2),