sincos_timesim.vhd

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      O => count_0_Q
    );
  count_0_D_44 : X_XOR2
    port map (
      I0 => NlwInverterSignal_count_0_D_IN0,
      I1 => count_0_D2,
      O => count_0_D
    );
  count_0_D1_45 : X_ZERO
    port map (
      O => count_0_D1
    );
  count_0_D2_46 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_0_D2_IN0,
      I1 => NlwInverterSignal_count_0_D2_IN1,
      I2 => count(2),
      I3 => NlwInverterSignal_count_0_D2_IN3,
      I4 => NlwInverterSignal_count_0_D2_IN4,
      I5 => count(5),
      I6 => NlwInverterSignal_count_0_D2_IN6,
      O => count_0_D2
    );
  count_0_CLKF_47 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => count_0_CLKF
    );
  count_4_Q_48 : X_BUF
    port map (
      I => count_4_Q,
      O => count(4)
    );
  count_4_tsimcreated_xor_Q_49 : X_XOR2
    port map (
      I0 => count_4_D,
      I1 => count_4_Q,
      O => count_4_tsimcreated_xor_Q
    );
  count_4_REG : X_FF
    port map (
      I => count_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => count_4_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => count_4_Q
    );
  count_4_D_50 : X_XOR2
    port map (
      I0 => count_4_D1,
      I1 => count_4_D2,
      O => count_4_D
    );
  count_4_D1_51 : X_ZERO
    port map (
      O => count_4_D1
    );
  count_4_D2_52 : X_AND4
    port map (
      I0 => count(1),
      I1 => count(0),
      I2 => count(2),
      I3 => count(3),
      O => count_4_D2
    );
  count_4_CLKF_53 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => count_4_CLKF
    );
  count_5_Q_54 : X_BUF
    port map (
      I => count_5_Q,
      O => count(5)
    );
  count_5_tsimcreated_xor_Q_55 : X_XOR2
    port map (
      I0 => count_5_D,
      I1 => count_5_Q,
      O => count_5_tsimcreated_xor_Q
    );
  count_5_REG : X_FF
    port map (
      I => count_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => count_5_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => count_5_Q
    );
  count_5_D_56 : X_XOR2
    port map (
      I0 => count_5_D1,
      I1 => count_5_D2,
      O => count_5_D
    );
  count_5_D1_57 : X_ZERO
    port map (
      O => count_5_D1
    );
  count_5_D2_PT_0_58 : X_AND5
    port map (
      I0 => count(1),
      I1 => count(0),
      I2 => count(2),
      I3 => count(3),
      I4 => count(4),
      O => count_5_D2_PT_0
    );
  count_5_D2_PT_1_59 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_5_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_5_D2_PT_1_IN1,
      I2 => count(2),
      I3 => NlwInverterSignal_count_5_D2_PT_1_IN3,
      I4 => NlwInverterSignal_count_5_D2_PT_1_IN4,
      I5 => count(5),
      I6 => NlwInverterSignal_count_5_D2_PT_1_IN6,
      O => count_5_D2_PT_1
    );
  count_5_D2_60 : X_OR2
    port map (
      I0 => count_5_D2_PT_0,
      I1 => count_5_D2_PT_1,
      O => count_5_D2
    );
  count_5_CLKF_61 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => count_5_CLKF
    );
  dount_0_Q_62 : X_BUF
    port map (
      I => dount_0_Q,
      O => dount(0)
    );
  dount_0_EXP_63 : X_BUF
    port map (
      I => dount_0_EXP_tsimrenamed_net_Q,
      O => dount_0_EXP
    );
  dount_0_tsimcreated_xor_Q_64 : X_XOR2
    port map (
      I0 => dount_0_D,
      I1 => dount_0_Q,
      O => dount_0_tsimcreated_xor_Q
    );
  dount_0_REG : X_FF
    port map (
      I => dount_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dount_0_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => dount_0_Q
    );
  dount_0_D_65 : X_XOR2
    port map (
      I0 => dount_0_D1,
      I1 => dount_0_D2,
      O => dount_0_D
    );
  dount_0_D1_66 : X_ZERO
    port map (
      O => dount_0_D1
    );
  dount_0_D2_67 : X_ONE
    port map (
      O => dount_0_D2
    );
  dount_0_CLKF_68 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => dount_0_CLKF
    );
  dount_0_EXP_PT_0_69 : X_AND5
    port map (
      I0 => count(1),
      I1 => count(0),
      I2 => count(2),
      I3 => count(3),
      I4 => data_tmp(5),
      O => dount_0_EXP_PT_0
    );
  dount_0_EXP_PT_1_70 : X_AND7
    port map (
      I0 => count(1),
      I1 => NlwInverterSignal_dount_0_EXP_PT_1_IN1,
      I2 => count(2),
      I3 => NlwInverterSignal_dount_0_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_dount_0_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_dount_0_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_dount_0_EXP_PT_1_IN6,
      O => dount_0_EXP_PT_1
    );
  dount_0_EXP_PT_2_71 : X_AND7
    port map (
      I0 => NlwInverterSignal_dount_0_EXP_PT_2_IN0,
      I1 => count(0),
      I2 => count(2),
      I3 => NlwInverterSignal_dount_0_EXP_PT_2_IN3,
      I4 => NlwInverterSignal_dount_0_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_dount_0_EXP_PT_2_IN5,
      I6 => NlwInverterSignal_dount_0_EXP_PT_2_IN6,
      O => dount_0_EXP_PT_2
    );
  dount_0_EXP_PT_3_72 : X_AND7
    port map (
      I0 => NlwInverterSignal_dount_0_EXP_PT_3_IN0,
      I1 => count(0),
      I2 => NlwInverterSignal_dount_0_EXP_PT_3_IN2,
      I3 => count(3),
      I4 => NlwInverterSignal_dount_0_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_dount_0_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_dount_0_EXP_PT_3_IN6,
      O => dount_0_EXP_PT_3
    );
  dount_0_EXP_tsimrenamed_net_Q_73 : X_OR4
    port map (
      I0 => dount_0_EXP_PT_0,
      I1 => dount_0_EXP_PT_1,
      I2 => dount_0_EXP_PT_2,
      I3 => dount_0_EXP_PT_3,
      O => dount_0_EXP_tsimrenamed_net_Q
    );
  count_6_Q_74 : X_BUF
    port map (
      I => count_6_Q,
      O => count(6)
    );
  count_6_EXP_75 : X_BUF
    port map (
      I => count_6_EXP_tsimrenamed_net_Q,
      O => count_6_EXP
    );
  count_6_tsimcreated_xor_Q_76 : X_XOR2
    port map (
      I0 => count_6_D,
      I1 => count_6_Q,
      O => count_6_tsimcreated_xor_Q
    );
  count_6_REG : X_FF
    port map (
      I => count_6_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => count_6_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => count_6_Q
    );
  count_6_D_77 : X_XOR2
    port map (
      I0 => count_6_D1,
      I1 => count_6_D2,
      O => count_6_D
    );
  count_6_D1_78 : X_ZERO
    port map (
      O => count_6_D1
    );
  count_6_D2_79 : X_AND6
    port map (
      I0 => count(1),
      I1 => count(0),
      I2 => count(2),
      I3 => count(3),
      I4 => count(4),
      I5 => count(5),
      O => count_6_D2
    );
  count_6_CLKF_80 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => count_6_CLKF
    );
  count_6_EXP_tsimrenamed_net_Q_81 : X_AND8
    port map (
      I0 => count(1),
      I1 => NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN1,
      I2 => count(2),
      I3 => NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN3,
      I4 => NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN5,
      I6 => NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN6,
      I7 => NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN7,
      O => count_6_EXP_tsimrenamed_net_Q
    );
  dount_1_Q_82 : X_BUF
    port map (
      I => dount_1_Q,
      O => dount(1)
    );
  dount_1_EXP_83 : X_BUF
    port map (
      I => dount_1_EXP_tsimrenamed_net_Q,
      O => dount_1_EXP
    );
  dount_1_tsimcreated_xor_Q_84 : X_XOR2
    port map (
      I0 => dount_1_D,
      I1 => dount_1_Q,
      O => dount_1_tsimcreated_xor_Q
    );
  dount_1_REG : X_FF
    port map (
      I => dount_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => dount_1_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => dount_1_Q
    );
  dount_1_D_85 : X_XOR2
    port map (
      I0 => dount_1_D1,
      I1 => dount_1_D2,
      O => dount_1_D
    );
  dount_1_D1_86 : X_ZERO
    port map (
      O => dount_1_D1
    );
  dount_1_D2_87 : X_AND2
    port map (
      I0 => dount(0),
      I1 => dount(0),
      O => dount_1_D2
    );
  dount_1_CLKF_88 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => dount_1_CLKF
    );
  dount_1_EXP_PT_0_89 : X_AND8
    port map (
      I0 => count(1),
      I1 => count(0),
      I2 => NlwInverterSignal_dount_1_EXP_PT_0_IN2,
      I3 => count(3),
      I4 => NlwInverterSignal_dount_1_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_dount_1_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_dount_1_EXP_PT_0_IN6,
      I7 => NlwInverterSignal_dount_1_EXP_PT_0_IN7,
      O => dount_1_EXP_PT_0
    );
  dount_1_EXP_PT_1_90 : X_AND8
    port map (
      I0 => count(1),
      I1 => NlwInverterSignal_dount_1_EXP_PT_1_IN1,
      I2 => count(2),
      I3 => count(3),
      I4 => NlwInverterSignal_dount_1_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_dount_1_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_dount_1_EXP_PT_1_IN6,
      I7 => address_tmp(2),
      O => dount_1_EXP_PT_1
    );
  dount_1_EXP_tsimrenamed_net_Q_91 : X_OR2
    port map (
      I0 => dount_1_EXP_PT_0,
      I1 => dount_1_EXP_PT_1,
      O => dount_1_EXP_tsimrenamed_net_Q
    );
  dount_2_Q_92 : X_BUF
    port map (
      I => dount_2_Q,
      O => dount(2)