sincos_timesim.vhd

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

  signal NlwInverterSignal_a_0_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_a_3_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_a_3_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_a_3_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_a_3_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_a_3_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_a_5_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_io_ud_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_io_ud_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_io_ud_OBUF_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_io_ud_OBUF_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_io_ud_OBUF_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_io_ud_OBUF_D2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_mst_rst_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_wrb_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_wrb_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN7 : STD_LOGIC; 
  signal count : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal data_tmp : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal dount : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal address_tmp : STD_LOGIC_VECTOR ( 5 downto 0 ); 
begin
  clk_IBUF_0 : X_BUF
    port map (
      I => clk,
      O => clk_IBUF
    );
  a_0_Q_1 : X_BUF
    port map (
      I => a_0,
      O => a(0)
    );
  a_1_Q_2 : X_BUF
    port map (
      I => a_1,
      O => a(1)
    );
  a_2_Q_3 : X_BUF
    port map (
      I => a_2,
      O => a(2)
    );
  a_3_Q_4 : X_BUF
    port map (
      I => a_3,
      O => a(3)
    );
  a_4_Q_5 : X_BUF
    port map (
      I => a_4,
      O => a(4)
    );
  a_5_Q_6 : X_BUF
    port map (
      I => a_5,
      O => a(5)
    );
  d_0_Q_7 : X_BUF
    port map (
      I => d_0,
      O => d(0)
    );
  d_1_Q_8 : X_BUF
    port map (
      I => d_1,
      O => d(1)
    );
  d_2_Q_9 : X_BUF
    port map (
      I => d_2,
      O => d(2)
    );
  d_3_Q_10 : X_BUF
    port map (
      I => d_3,
      O => d(3)
    );
  d_4_Q_11 : X_BUF
    port map (
      I => d_4,
      O => d(4)
    );
  d_5_Q_12 : X_BUF
    port map (
      I => d_5,
      O => d(5)
    );
  d_6_Q_13 : X_BUF
    port map (
      I => d_6,
      O => d(6)
    );
  d_7_Q_14 : X_BUF
    port map (
      I => d_7,
      O => d(7)
    );
  io_ud_15 : X_BUF
    port map (
      I => io_ud_OBUF,
      O => io_ud
    );
  mst_rst_16 : X_BUF
    port map (
      I => mst_rst_OBUF,
      O => mst_rst
    );
  wrb_17 : X_BUF
    port map (
      I => wrb_OBUF,
      O => wrb
    );
  count_2_Q_18 : X_BUF
    port map (
      I => count_2_Q,
      O => count(2)
    );
  count_2_tsimcreated_xor_Q_19 : X_XOR2
    port map (
      I0 => count_2_D,
      I1 => count_2_Q,
      O => count_2_tsimcreated_xor_Q
    );
  count_2_REG : X_FF
    port map (
      I => count_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => count_2_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => count_2_Q
    );
  Gnd_20 : X_ZERO
    port map (
      O => Gnd
    );
  Vcc_21 : X_ONE
    port map (
      O => Vcc
    );
  count_2_D_22 : X_XOR2
    port map (
      I0 => count_2_D1,
      I1 => count_2_D2,
      O => count_2_D
    );
  count_2_D1_23 : X_ZERO
    port map (
      O => count_2_D1
    );
  count_2_D2_PT_0_24 : X_AND2
    port map (
      I0 => count(1),
      I1 => count(0),
      O => count_2_D2_PT_0
    );
  count_2_D2_PT_1_25 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_2_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_2_D2_PT_1_IN1,
      I2 => count(2),
      I3 => NlwInverterSignal_count_2_D2_PT_1_IN3,
      I4 => NlwInverterSignal_count_2_D2_PT_1_IN4,
      I5 => count(5),
      I6 => NlwInverterSignal_count_2_D2_PT_1_IN6,
      O => count_2_D2_PT_1
    );
  count_2_D2_26 : X_OR2
    port map (
      I0 => count_2_D2_PT_0,
      I1 => count_2_D2_PT_1,
      O => count_2_D2
    );
  count_2_CLKF_27 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => count_2_CLKF
    );
  count_3_Q_28 : X_BUF
    port map (
      I => count_3_Q,
      O => count(3)
    );
  count_3_tsimcreated_xor_Q_29 : X_XOR2
    port map (
      I0 => count_3_D,
      I1 => count_3_Q,
      O => count_3_tsimcreated_xor_Q
    );
  count_3_REG : X_FF
    port map (
      I => count_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => count_3_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => count_3_Q
    );
  count_3_D_30 : X_XOR2
    port map (
      I0 => count_3_D1,
      I1 => count_3_D2,
      O => count_3_D
    );
  count_3_D1_31 : X_ZERO
    port map (
      O => count_3_D1
    );
  count_3_D2_32 : X_AND3
    port map (
      I0 => count(1),
      I1 => count(0),
      I2 => count(2),
      O => count_3_D2
    );
  count_3_CLKF_33 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => count_3_CLKF
    );
  count_1_Q_34 : X_BUF
    port map (
      I => count_1_Q,
      O => count(1)
    );
  count_1_EXP_35 : X_BUF
    port map (
      I => count_1_EXP_tsimrenamed_net_Q,
      O => count_1_EXP
    );
  count_1_tsimcreated_xor_Q_36 : X_XOR2
    port map (
      I0 => count_1_D,
      I1 => count_1_Q,
      O => count_1_tsimcreated_xor_Q
    );
  count_1_REG : X_FF
    port map (
      I => count_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => count_1_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => count_1_Q
    );
  count_1_D_37 : X_XOR2
    port map (
      I0 => count_1_D1,
      I1 => count_1_D2,
      O => count_1_D
    );
  count_1_D1_38 : X_ZERO
    port map (
      O => count_1_D1
    );
  count_1_D2_39 : X_AND2
    port map (
      I0 => count(0),
      I1 => count(0),
      O => count_1_D2
    );
  count_1_CLKF_40 : X_AND2
    port map (
      I0 => clk_IBUF,
      I1 => clk_IBUF,
      O => count_1_CLKF
    );
  count_1_EXP_tsimrenamed_net_Q_41 : X_AND8
    port map (
      I0 => count(1),
      I1 => count(0),
      I2 => NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN2,
      I3 => count(3),
      I4 => NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN5,
      I6 => NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN6,
      I7 => data_tmp(2),
      O => count_1_EXP_tsimrenamed_net_Q
    );
  count_0_Q_42 : X_BUF
    port map (
      I => count_0_Q,
      O => count(0)
    );
  count_0_tsimcreated_xor_Q_43 : X_XOR2
    port map (
      I0 => count_0_D,
      I1 => count_0_Q,
      O => count_0_tsimcreated_xor_Q
    );
  count_0_REG : X_FF
    port map (
      I => count_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => count_0_CLKF,
      SET => Gnd,
      RST => PRLD,