sincos_timesim.vhd

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

  signal a_5_D2 : STD_LOGIC; 
  signal a_5_EXP_PT_0 : STD_LOGIC; 
  signal a_5_EXP_PT_1 : STD_LOGIC; 
  signal d_0_Q : STD_LOGIC; 
  signal d_0_D : STD_LOGIC; 
  signal d_0_CLKF : STD_LOGIC; 
  signal d_0_D1 : STD_LOGIC; 
  signal d_0_D2 : STD_LOGIC; 
  signal d_1_Q : STD_LOGIC; 
  signal d_1_D : STD_LOGIC; 
  signal d_1_CLKF : STD_LOGIC; 
  signal d_1_D1 : STD_LOGIC; 
  signal d_1_D2 : STD_LOGIC; 
  signal d_2_Q : STD_LOGIC; 
  signal d_2_D : STD_LOGIC; 
  signal d_2_CLKF : STD_LOGIC; 
  signal d_2_D1 : STD_LOGIC; 
  signal d_2_D2 : STD_LOGIC; 
  signal d_3_Q : STD_LOGIC; 
  signal d_3_D : STD_LOGIC; 
  signal d_3_CLKF : STD_LOGIC; 
  signal d_3_D1 : STD_LOGIC; 
  signal d_3_D2 : STD_LOGIC; 
  signal d_4_Q : STD_LOGIC; 
  signal d_4_D : STD_LOGIC; 
  signal d_4_CLKF : STD_LOGIC; 
  signal d_4_D1 : STD_LOGIC; 
  signal d_4_D2 : STD_LOGIC; 
  signal d_5_Q : STD_LOGIC; 
  signal d_5_D : STD_LOGIC; 
  signal d_5_CLKF : STD_LOGIC; 
  signal d_5_D1 : STD_LOGIC; 
  signal d_5_D2 : STD_LOGIC; 
  signal d_6_Q : STD_LOGIC; 
  signal d_6_D : STD_LOGIC; 
  signal d_6_CLKF : STD_LOGIC; 
  signal d_6_D1 : STD_LOGIC; 
  signal d_6_D2 : STD_LOGIC; 
  signal d_7_Q : STD_LOGIC; 
  signal d_7_D : STD_LOGIC; 
  signal d_7_CLKF : STD_LOGIC; 
  signal d_7_D1 : STD_LOGIC; 
  signal d_7_D2 : STD_LOGIC; 
  signal io_ud_OBUF_Q : STD_LOGIC; 
  signal io_ud_OBUF_D : STD_LOGIC; 
  signal io_ud_OBUF_CLKF : STD_LOGIC; 
  signal io_ud_OBUF_D1 : STD_LOGIC; 
  signal io_ud_OBUF_D2 : STD_LOGIC; 
  signal mst_rst_OBUF_Q : STD_LOGIC; 
  signal mst_rst_OBUF_D : STD_LOGIC; 
  signal mst_rst_OBUF_CLKF : STD_LOGIC; 
  signal mst_rst_OBUF_D1 : STD_LOGIC; 
  signal mst_rst_OBUF_D2 : STD_LOGIC; 
  signal mst_rst_OBUF_D2_PT_0 : STD_LOGIC; 
  signal mst_rst_OBUF_D2_PT_1 : STD_LOGIC; 
  signal wrb_OBUF_Q : STD_LOGIC; 
  signal wrb_OBUF_D : STD_LOGIC; 
  signal wrb_OBUF_D1 : STD_LOGIC; 
  signal wrb_OBUF_D2 : STD_LOGIC; 
  signal EXP10_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP10_EXP_PT_0 : STD_LOGIC; 
  signal EXP10_EXP_PT_1 : STD_LOGIC; 
  signal EXP10_EXP_PT_2 : STD_LOGIC; 
  signal EXP10_EXP_PT_3 : STD_LOGIC; 
  signal EXP10_EXP_PT_4 : STD_LOGIC; 
  signal EXP11_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP11_EXP_PT_0 : STD_LOGIC; 
  signal EXP11_EXP_PT_1 : STD_LOGIC; 
  signal EXP11_EXP_PT_2 : STD_LOGIC; 
  signal EXP11_EXP_PT_3 : STD_LOGIC; 
  signal EXP12_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP12_EXP_PT_0 : STD_LOGIC; 
  signal EXP12_EXP_PT_1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dount_0_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_count_6_EXP_tsimrenamed_net_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dount_1_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_0_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_1_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_2_EXP_tsimrenamed_net_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_3_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_4_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_address_tmp_5_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_0_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_1_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_2_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_3_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_4_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_5_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_5_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_6_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_data_tmp_7_EXP_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_EXP_PT_2_IN1 : STD_LOGIC;