📄 sincos.rpt
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data_tmp<3> 8 3<- 0 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: address_tmp<2> 5: count<2> 9: data_tmp<2>
2: clk 6: count<3> 10: data_tmp<3>
3: count<0> 7: count<4> 11: data_tmp<4>
4: count<1> 8: count<5> 12: data_tmp<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
data_tmp<2> .XXXXXXXX............................... 8
d<2> .X......X............................... 2
dount<4> .X...................................... 1
dount<3> .X...................................... 1
dount<2> .X...................................... 1
address_tmp<2> XXXXXXXX................................ 8
data_tmp<6> .XXXXXXX...X............................ 8
dount<5> .X...................................... 1
data_tmp<4> .XXXXXXX..X............................. 8
data_tmp<3> .XXXXXXX.X.............................. 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 11/43
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\2 3 FB4_1 118 I/O (b)
(unused) 0 0 0 5 FB4_2 126 I/O
(unused) 0 0 0 5 FB4_3 133 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 128 I/O I
(unused) 0 0 0 5 FB4_6 129 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 130 I/O
(unused) 0 0 0 5 FB4_9 131 I/O
(unused) 0 0 0 5 FB4_10 135 I/O
(unused) 0 0 0 5 FB4_11 132 I/O
(unused) 0 0 0 5 FB4_12 134 I/O
(unused) 0 0 0 5 FB4_13 137 I/O
(unused) 0 0 0 5 FB4_14 136 I/O
data_tmp<5> 5 0 0 0 FB4_15 138 I/O (b)
data_tmp<0> 5 0 0 0 FB4_16 139 I/O (b)
data_tmp<7> 6 1<- 0 0 FB4_17 140 I/O (b)
address_tmp<4> 6 2<- /\1 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: address_tmp<4> 5: count<2> 9: data_tmp<0>
2: clk 6: count<3> 10: data_tmp<5>
3: count<0> 7: count<4> 11: data_tmp<7>
4: count<1> 8: count<5>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
data_tmp<5> .XXXXXXX.X.............................. 8
data_tmp<0> .X.XXXXXX............................... 7
data_tmp<7> .XXXXXXX..X............................. 8
address_tmp<4> XXXXXXXX................................ 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 7/47
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 52 I/O
(unused) 0 0 0 5 FB5_3 59 I/O
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O
(unused) 0 0 0 5 FB5_6 54 I/O
(unused) 0 0 0 5 FB5_7 66 I/O
(unused) 0 0 0 5 FB5_8 56 I/O
(unused) 0 0 0 5 FB5_9 57 I/O
(unused) 0 0 0 5 FB5_10 68 I/O
(unused) 0 0 0 5 FB5_11 58 I/O
(unused) 0 0 0 5 FB5_12 60 I/O
(unused) 0 0 0 5 FB5_13 70 I/O
(unused) 0 0 0 5 FB5_14 61 I/O
(unused) 0 0 0 5 FB5_15 64 I/O
(unused) 0 0 0 5 FB5_16 (b)
dount<1> 2 0 0 3 FB5_17 69 I/O (b)
dount<0> 3 0 0 2 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 4: dount<2> 6: dount<4>
2: dount<0> 5: dount<3> 7: dount<5>
3: dount<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dount<1> XXXXXXX................................. 7
dount<0> XXXXXXX................................. 7
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 106 I/O
(unused) 0 0 0 5 FB6_3 (b)
(unused) 0 0 0 5 FB6_4 111 I/O
(unused) 0 0 0 5 FB6_5 110 I/O
(unused) 0 0 0 5 FB6_6 112 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 113 I/O
(unused) 0 0 0 5 FB6_9 116 I/O
(unused) 0 0 0 5 FB6_10 115 I/O
(unused) 0 0 0 5 FB6_11 119 I/O
(unused) 0 0 0 5 FB6_12 120 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 121 I/O
(unused) 0 0 0 5 FB6_15 124 I/O
(unused) 0 0 0 5 FB6_16 117 I/O
(unused) 0 0 0 5 FB6_17 125 I/O
(unused) 0 0 0 5 FB6_18 (b)
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 71 I/O
(unused) 0 0 0 5 FB7_3 75 I/O
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 74 I/O
(unused) 0 0 0 5 FB7_6 76 I/O
(unused) 0 0 0 5 FB7_7 77 I/O
(unused) 0 0 0 5 FB7_8 78 I/O
(unused) 0 0 0 5 FB7_9 80 I/O
(unused) 0 0 0 5 FB7_10 79 I/O
(unused) 0 0 0 5 FB7_11 82 I/O
(unused) 0 0 0 5 FB7_12 85 I/O
(unused) 0 0 0 5 FB7_13 81 I/O
(unused) 0 0 0 5 FB7_14 86 I/O
(unused) 0 0 0 5 FB7_15 87 I/O
(unused) 0 0 0 5 FB7_16 83 I/O
(unused) 0 0 0 5 FB7_17 88 I/O
(unused) 0 0 0 5 FB7_18 (b)
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
(unused) 0 0 0 5 FB8_2 91 I/O
(unused) 0 0 0 5 FB8_3 95 I/O
(unused) 0 0 0 5 FB8_4 97 I/O
(unused) 0 0 0 5 FB8_5 92 I/O
(unused) 0 0 0 5 FB8_6 93 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 94 I/O
(unused) 0 0 0 5 FB8_9 96 I/O
(unused) 0 0 0 5 FB8_10 101 I/O
(unused) 0 0 0 5 FB8_11 98 I/O
(unused) 0 0 0 5 FB8_12 100 I/O
(unused) 0 0 0 5 FB8_13 103 I/O
(unused) 0 0 0 5 FB8_14 102 I/O
(unused) 0 0 0 5 FB8_15 104 I/O
(unused) 0 0 0 5 FB8_16 107 I/O
(unused) 0 0 0 5 FB8_17 105 I/O
(unused) 0 0 0 5 FB8_18 (b)
******************************* Equations ********************************
********** Mapped Logic **********
FDCPE_a0: FDCPE port map (a(0),address_tmp(0),clk,'0','0');
FDCPE_a1: FDCPE port map (a(1),address_tmp(1),clk,'0','0');
FDCPE_a2: FDCPE port map (a(2),address_tmp(2),clk,'0','0');
FDCPE_a3: FDCPE port map (a(3),address_tmp(3),clk,'0','0');
FDCPE_a4: FDCPE port map (a(4),address_tmp(4),clk,'0','0');
FDCPE_a5: FDCPE port map (a(5),address_tmp(5),clk,'0','0');
FDCPE_address_tmp0: FDCPE port map (address_tmp(0),address_tmp_D(0),clk,'0','0');
address_tmp_D(0) <= ((count(4).EXP)
OR (a_0.EXP)
OR (count(4) AND address_tmp(0))
OR (count(5) AND address_tmp(0))
OR (NOT count(2) AND NOT count(3) AND address_tmp(0))
OR (count(2) AND count(3) AND count(1) AND address_tmp(0)));
FDCPE_address_tmp1: FDCPE port map (address_tmp(1),address_tmp_D(1),clk,'0','0');
address_tmp_D(1) <= ((wrb_OBUF.EXP)
OR (count(4) AND address_tmp(1))
OR (count(5) AND address_tmp(1))
OR (count(2) AND count(1) AND address_tmp(1))
OR (NOT count(2) AND NOT count(3) AND address_tmp(1)));
FTCPE_address_tmp2: FTCPE port map (address_tmp(2),address_tmp_T(2),clk,'0','0');
address_tmp_T(2) <= ((dount(2).EXP)
OR (count(2) AND NOT count(3) AND NOT count(4) AND NOT count(5) AND
NOT address_tmp(2))
OR (count(3) AND NOT count(1) AND count(0) AND NOT count(4) AND
NOT count(5) AND address_tmp(2)));
FTCPE_address_tmp3: FTCPE port map (address_tmp(3),address_tmp_T(3),clk,'0','0');
address_tmp_T(3) <= ((count(2) AND NOT count(3) AND NOT count(4) AND NOT count(5) AND
address_tmp(3))
OR (NOT count(2) AND count(3) AND NOT count(4) AND NOT count(5) AND
NOT address_tmp(3))
OR (count(2) AND NOT count(1) AND count(0) AND NOT count(4) AND
NOT count(5) AND address_tmp(3))
OR (count(3) AND NOT count(1) AND NOT count(0) AND NOT count(4) AND
NOT count(5) AND NOT address_tmp(3)));
FTCPE_address_tmp4: FTCPE port map (address_tmp(4),address_tmp_T(4),clk,'0','0');
address_tmp_T(4) <= ((EXP12_.EXP)
OR (count(2) AND NOT count(3) AND NOT count(4) AND NOT count(5) AND
address_tmp(4))
OR (NOT count(2) AND count(3) AND NOT count(1) AND NOT count(4) AND
NOT count(5) AND address_tmp(4))
OR (count(3) AND NOT count(1) AND count(0) AND NOT count(4) AND
NOT count(5) AND address_tmp(4)));
FTCPE_address_tmp5: FTCPE port map (address_tmp(5),address_tmp_T(5),clk,'0','0');
address_tmp_T(5) <= ((count(2) AND NOT count(3) AND NOT count(4) AND NOT count(5) AND
address_tmp(5))
OR (NOT count(2) AND count(3) AND NOT count(4) AND NOT count(5) AND
address_tmp(5))
OR (count(2) AND NOT count(1) AND NOT count(0) AND NOT count(4) AND
NOT count(5) AND address_tmp(5))
OR (count(2) AND count(3) AND NOT count(1) AND count(0) AND
NOT count(4) AND NOT count(5) AND NOT address_tmp(5)));
FTCPE_count0: FTCPE port map (count(0),count_T(0),clk,'0','0');
count_T(0) <= (count(2) AND NOT count(3) AND NOT count(1) AND NOT count(0) AND
NOT count(4) AND count(5));
FTCPE_count1: FTCPE port map (count(1),count(0),clk,'0','0');
FTCPE_count2: FTCPE port map (count(2),count_T(2),clk,'0','0');
count_T(2) <= ((count(1) AND count(0))
OR (count(2) AND NOT count(3) AND NOT count(1) AND NOT count(0) AND
NOT count(4) AND count(5)));
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