da1_test.qsf

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Full Version
# Date created = 10:41:38  July 18, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		da1_test_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY da1_test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:41:38  JULY 18, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"

set_location_assignment PIN_153 -to clk

set_location_assignment PIN_20 -to mst_rst

set_location_assignment PIN_12 -to d[0]
set_location_assignment PIN_7 -to d[1]
set_location_assignment PIN_14 -to d[2]
set_location_assignment PIN_13 -to d[3]
set_location_assignment PIN_16 -to d[4]
set_location_assignment PIN_15 -to d[5]
set_location_assignment PIN_18 -to d[6]
set_location_assignment PIN_17 -to d[7]

set_location_assignment PIN_2 -to a[0]
set_location_assignment PIN_1 -to a[1]
set_location_assignment PIN_4 -to a[2]
set_location_assignment PIN_3 -to a[3]
set_location_assignment PIN_6 -to a[4]
set_location_assignment PIN_5 -to a[5]

set_location_assignment PIN_238 -to wrb

set_location_assignment PIN_237 -to io_ud

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"