prev_cmp_da1_test.tan.qmsg

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[5\] register address_tmp\[5\] 172.12 MHz 5.81 ns Internal " "Info: Clock \"clk\" has Internal fmax of 172.12 MHz between source register \"count\[5\]\" and destination register \"address_tmp\[5\]\" (period= 5.81 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.549 ns + Longest register register " "Info: + Longest register to register delay is 5.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[5\] 1 REG LC_X30_Y15_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y15_N4; Fanout = 8; REG Node = 'count\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.442 ns) 0.975 ns Equal2~4 2 COMB LC_X30_Y15_N7 7 " "Info: 2: + IC(0.533 ns) + CELL(0.442 ns) = 0.975 ns; Loc. = LC_X30_Y15_N7; Fanout = 7; COMB Node = 'Equal2~4'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { count[5] Equal2~4 } "NODE_NAME" } } { "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.292 ns) 2.854 ns Equal3~2 3 COMB LC_X29_Y16_N7 5 " "Info: 3: + IC(1.587 ns) + CELL(0.292 ns) = 2.854 ns; Loc. = LC_X29_Y16_N7; Fanout = 5; COMB Node = 'Equal3~2'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.879 ns" { Equal2~4 Equal3~2 } "NODE_NAME" } } { "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.590 ns) 3.884 ns address_tmp~65 4 COMB LC_X29_Y16_N9 6 " "Info: 4: + IC(0.440 ns) + CELL(0.590 ns) = 3.884 ns; Loc. = LC_X29_Y16_N9; Fanout = 6; COMB Node = 'address_tmp~65'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.030 ns" { Equal3~2 address_tmp~65 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.478 ns) 5.549 ns address_tmp\[5\] 5 REG LC_X32_Y16_N2 2 " "Info: 5: + IC(1.187 ns) + CELL(0.478 ns) = 5.549 ns; Loc. = LC_X32_Y16_N2; Fanout = 2; REG Node = 'address_tmp\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.665 ns" { address_tmp~65 address_tmp[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns ( 32.47 % ) " "Info: Total cell delay = 1.802 ns ( 32.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.747 ns ( 67.53 % ) " "Info: Total interconnect delay = 3.747 ns ( 67.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.549 ns" { count[5] Equal2~4 Equal3~2 address_tmp~65 address_tmp[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.549 ns" { count[5] {} Equal2~4 {} Equal3~2 {} address_tmp~65 {} address_tmp[5] {} } { 0.000ns 0.533ns 1.587ns 0.440ns 1.187ns } { 0.000ns 0.442ns 0.292ns 0.590ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns address_tmp\[5\] 2 REG LC_X32_Y16_N2 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y16_N2; Fanout = 2; REG Node = 'address_tmp\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk address_tmp[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk address_tmp[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} address_tmp[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns count\[5\] 2 REG LC_X30_Y15_N4 8 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X30_Y15_N4; Fanout = 8; REG Node = 'count\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk count[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk count[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} count[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk address_tmp[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} address_tmp[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk count[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} count[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.549 ns" { count[5] Equal2~4 Equal3~2 address_tmp~65 address_tmp[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.549 ns" { count[5] {} Equal2~4 {} Equal3~2 {} address_tmp~65 {} address_tmp[5] {} } { 0.000ns 0.533ns 1.587ns 0.440ns 1.187ns } { 0.000ns 0.442ns 0.292ns 0.590ns 0.478ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk address_tmp[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} address_tmp[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk count[5] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} count[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk a\[4\] a\[4\]~reg0 9.596 ns register " "Info: tco from clock \"clk\" to destination pin \"a\[4\]\" through register \"a\[4\]~reg0\" is 9.596 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns a\[4\]~reg0 2 REG LC_X32_Y16_N0 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y16_N0; Fanout = 1; REG Node = 'a\[4\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk a[4]~reg0 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 66 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk a[4]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} a[4]~reg0 {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 66 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.410 ns + Longest register pin " "Info: + Longest register to pin delay is 6.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[4\]~reg0 1 REG LC_X32_Y16_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y16_N0; Fanout = 1; REG Node = 'a\[4\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[4]~reg0 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 66 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(2.124 ns) 6.410 ns a\[4\] 2 PIN PIN_5 0 " "Info: 2: + IC(4.286 ns) + CELL(2.124 ns) = 6.410 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'a\[4\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.410 ns" { a[4]~reg0 a[4] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 33.14 % ) " "Info: Total cell delay = 2.124 ns ( 33.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.286 ns ( 66.86 % ) " "Info: Total interconnect delay = 4.286 ns ( 66.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.410 ns" { a[4]~reg0 a[4] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.410 ns" { a[4]~reg0 {} a[4] {} } { 0.000ns 4.286ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk a[4]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} a[4]~reg0 {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.410 ns" { a[4]~reg0 a[4] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.410 ns" { a[4]~reg0 {} a[4] {} } { 0.000ns 4.286ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk wrb 5.218 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"wrb\" is 5.218 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(2.108 ns) 5.218 ns wrb 2 PIN PIN_237 0 " "Info: 2: + IC(1.641 ns) + CELL(2.108 ns) = 5.218 ns; Loc. = PIN_237; Fanout = 0; PIN Node = 'wrb'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.749 ns" { clk wrb } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.577 ns ( 68.55 % ) " "Info: Total cell delay = 3.577 ns ( 68.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns ( 31.45 % ) " "Info: Total interconnect delay = 1.641 ns ( 31.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.218 ns" { clk wrb } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.218 ns" { clk {} clk~out0 {} wrb {} } { 0.000ns 0.000ns 1.641ns } { 0.000ns 1.469ns 2.108ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Peak virtual memory: 134 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 03 23:25:17 2011 " "Info: Processing ended: Sun Jul 03 23:25:17 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}