da1_test.fit.rpt

来自「2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种」· RPT 代码 · 共 501 行 · 第 1/5 页

; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+-------------------------+--------------------+
; Type                    ; Value              ;
+-------------------------+--------------------+
; Placement               ;                    ;
;     -- Requested        ; 0 / 97 ( 0.00 % )  ;
;     -- Achieved         ; 0 / 97 ( 0.00 % )  ;
;                         ;                    ;
; Routing (by Connection) ;                    ;
;     -- Requested        ; 0 / 0 ( 0.00 % )   ;
;     -- Achieved         ; 0 / 0 ( 0.00 % )   ;
+-------------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                       ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Top            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;          ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+


+--------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                             ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top            ; 97      ; 0                 ; N/A                     ; Source File       ;
+----------------+---------+-------------------+-------------------------+-------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/da1_test/da1_test.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 75 / 5,980 ( 1 % )   ;
;     -- Combinational with no register       ; 37                   ;
;     -- Register only                        ; 12                   ;
;     -- Combinational with a register        ; 26                   ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 33                   ;
;     -- 3 input functions                    ; 17                   ;
;     -- 2 input functions                    ; 12                   ;
;     -- 1 input functions                    ; 1                    ;
;     -- 0 input functions                    ; 0                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 66                   ;
;     -- arithmetic mode                      ; 9                    ;
;     -- qfbk mode                            ; 3                    ;
;     -- register cascade mode                ; 0                    ;
;     -- synchronous clear/load mode          ; 13                   ;
;     -- asynchronous clear/load mode         ; 0                    ;
;                                             ;                      ;
; Total registers                             ; 38 / 6,523 ( < 1 % ) ;
; Total LABs                                  ; 15 / 598 ( 3 % )     ;
; Logic elements in carry chains              ; 11                   ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 18 / 185 ( 10 % )    ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )       ;
; Global signals                              ; 1                    ;
; M4Ks                                        ; 0 / 20 ( 0 % )       ;
; Total memory bits                           ; 0 / 92,160 ( 0 % )   ;
; Total RAM block bits                        ; 0 / 92,160 ( 0 % )   ;