prev_cmp_da1_test.tan.qmsg

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count_clk\[3\] count_clk\[12\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"count_clk\[3\]\" and destination register \"count_clk\[12\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.491 ns + Longest register register " "Info: + Longest register to register delay is 2.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_clk\[3\] 1 REG LC_X2_Y18_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y18_N6; Fanout = 4; REG Node = 'count_clk\[3\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { count_clk[3] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns count_clk\[3\]~5COUT1_40 2 COMB LC_X2_Y18_N6 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X2_Y18_N6; Fanout = 2; COMB Node = 'count_clk\[3\]~5COUT1_40'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.098 ns" { count_clk[3] count_clk[3]~5COUT1_40 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns count_clk\[4\]~7COUT1_42 3 COMB LC_X2_Y18_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X2_Y18_N7; Fanout = 2; COMB Node = 'count_clk\[4\]~7COUT1_42'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { count_clk[3]~5COUT1_40 count_clk[4]~7COUT1_42 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns count_clk\[5\]~9COUT1_44 4 COMB LC_X2_Y18_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X2_Y18_N8; Fanout = 2; COMB Node = 'count_clk\[5\]~9COUT1_44'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { count_clk[4]~7COUT1_42 count_clk[5]~9COUT1_44 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.516 ns count_clk\[6\]~11 5 COMB LC_X2_Y18_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X2_Y18_N9; Fanout = 6; COMB Node = 'count_clk\[6\]~11'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { count_clk[5]~9COUT1_44 count_clk[6]~11 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.652 ns count_clk\[11\]~21 6 COMB LC_X2_Y17_N4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X2_Y17_N4; Fanout = 2; COMB Node = 'count_clk\[11\]~21'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { count_clk[6]~11 count_clk[11]~21 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.491 ns count_clk\[12\] 7 REG LC_X2_Y17_N5 4 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.491 ns; Loc. = LC_X2_Y17_N5; Fanout = 4; REG Node = 'count_clk\[12\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { count_clk[11]~21 count_clk[12] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.968 ns ( 79.00 % ) " "Info: Total cell delay = 1.968 ns ( 79.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.523 ns ( 21.00 % ) " "Info: Total interconnect delay = 0.523 ns ( 21.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.491 ns" { count_clk[3] count_clk[3]~5COUT1_40 count_clk[4]~7COUT1_42 count_clk[5]~9COUT1_44 count_clk[6]~11 count_clk[11]~21 count_clk[12] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.491 ns" { count_clk[3] {} count_clk[3]~5COUT1_40 {} count_clk[4]~7COUT1_42 {} count_clk[5]~9COUT1_44 {} count_clk[6]~11 {} count_clk[11]~21 {} count_clk[12] {} } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 28; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns count_clk\[12\] 2 REG LC_X2_Y17_N5 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N5; Fanout = 4; REG Node = 'count_clk\[12\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk count_clk[12] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk count_clk[12] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} count_clk[12] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 28; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns count_clk\[3\] 2 REG LC_X2_Y18_N6 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y18_N6; Fanout = 4; REG Node = 'count_clk\[3\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk count_clk[3] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk count_clk[3] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} count_clk[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk count_clk[12] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} count_clk[12] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk count_clk[3] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} count_clk[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.491 ns" { count_clk[3] count_clk[3]~5COUT1_40 count_clk[4]~7COUT1_42 count_clk[5]~9COUT1_44 count_clk[6]~11 count_clk[11]~21 count_clk[12] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.491 ns" { count_clk[3] {} count_clk[3]~5COUT1_40 {} count_clk[4]~7COUT1_42 {} count_clk[5]~9COUT1_44 {} count_clk[6]~11 {} count_clk[11]~21 {} count_clk[12] {} } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk count_clk[12] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} count_clk[12] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk count_clk[3] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} count_clk[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { count_clk[12] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { count_clk[12] {} } {  } {  } "" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 31 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk da1_d\[10\] da1_d\[10\]~reg0 7.178 ns register " "Info: tco from clock \"clk\" to destination pin \"da1_d\[10\]\" through register \"da1_d\[10\]~reg0\" is 7.178 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 28; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns da1_d\[10\]~reg0 2 REG LC_X3_Y17_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X3_Y17_N2; Fanout = 1; REG Node = 'da1_d\[10\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk da1_d[10]~reg0 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 42 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk da1_d[10]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} da1_d[10]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 42 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns da1_d\[10\]~reg0 1 REG LC_X3_Y17_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y17_N2; Fanout = 1; REG Node = 'da1_d\[10\]~reg0'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { da1_d[10]~reg0 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 42 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.876 ns) + CELL(2.124 ns) 4.000 ns da1_d\[10\] 2 PIN PIN_7 0 " "Info: 2: + IC(1.876 ns) + CELL(2.124 ns) = 4.000 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'da1_d\[10\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { da1_d[10]~reg0 da1_d[10] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "C:/A-基础实验(插针对接)(ALTERA)/09-DA输出实验/da1_test/da1_test.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 53.10 % ) " "Info: Total cell delay = 2.124 ns ( 53.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.876 ns ( 46.90 % ) " "Info: Total interconnect delay = 1.876 ns ( 46.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { da1_d[10]~reg0 da1_d[10] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.000 ns" { da1_d[10]~reg0 {} da1_d[10] {} } { 0.000ns 1.876ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk da1_d[10]~reg0 } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} da1_d[10]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { da1_d[10]~reg0 da1_d[10] } "NODE_NAME" } } { "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.000 ns" { da1_d[10]~reg0 {} da1_d[10] {} } { 0.000ns 1.876ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Peak virtual memory: 133 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 15 16:01:15 2011 " "Info: Processing ended: Tue Feb 15 16:01:15 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}