da1_test.fit.qmsg

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register count\[5\] register address_tmp\[0\] -4.508 ns " "Info: Slack time is -4.508 ns between source register \"count\[5\]\" and destination register \"address_tmp\[0\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.739 ns + Largest register register " "Info: + Largest register to register requirement is 0.739 ns" {  } {  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.931 ns   Shortest register " "Info:   Shortest clock path from clock \"clk\" to destination register is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.711 ns) 2.931 ns address_tmp\[0\] 2 REG Unassigned 2 " "Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = Unassigned; Fanout = 2; REG Node = 'address_tmp\[0\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk address_tmp[0] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.38 % ) " "Info: Total cell delay = 2.180 ns ( 74.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.751 ns ( 25.62 % ) " "Info: Total interconnect delay = 0.751 ns ( 25.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.931 ns   Longest register " "Info:   Longest clock path from clock \"clk\" to destination register is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.711 ns) 2.931 ns address_tmp\[0\] 2 REG Unassigned 2 " "Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = Unassigned; Fanout = 2; REG Node = 'address_tmp\[0\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk address_tmp[0] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.38 % ) " "Info: Total cell delay = 2.180 ns ( 74.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.751 ns ( 25.62 % ) " "Info: Total interconnect delay = 0.751 ns ( 25.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.931 ns   Shortest register " "Info:   Shortest clock path from clock \"clk\" to source register is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.711 ns) 2.931 ns count\[5\] 2 REG Unassigned 8 " "Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'count\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk count[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.38 % ) " "Info: Total cell delay = 2.180 ns ( 74.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.751 ns ( 25.62 % ) " "Info: Total interconnect delay = 0.751 ns ( 25.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.931 ns   Longest register " "Info:   Longest clock path from clock \"clk\" to source register is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK Unassigned 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = Unassigned; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.711 ns) 2.931 ns count\[5\] 2 REG Unassigned 8 " "Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'count\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk count[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.38 % ) " "Info: Total cell delay = 2.180 ns ( 74.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.751 ns ( 25.62 % ) " "Info: Total interconnect delay = 0.751 ns ( 25.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 22 -1 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns   " "Info:   Micro clock to output delay of source is 0.224 ns" {  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns   " "Info:   Micro setup delay of destination is 0.037 ns" {  } { { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.247 ns - Longest register register " "Info: - Longest register to register delay is 5.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[5\] 1 REG Unassigned 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 8; REG Node = 'count\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.114 ns) 0.782 ns Equal2~4 2 COMB Unassigned 7 " "Info: 2: + IC(0.668 ns) + CELL(0.114 ns) = 0.782 ns; Loc. = Unassigned; Fanout = 7; COMB Node = 'Equal2~4'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.782 ns" { count[5] Equal2~4 } "NODE_NAME" } } { "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.442 ns) 2.117 ns address_tmp~70 3 COMB Unassigned 1 " "Info: 3: + IC(0.893 ns) + CELL(0.442 ns) = 2.117 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'address_tmp~70'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { Equal2~4 address_tmp~70 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.292 ns) 3.776 ns address_tmp~71 4 COMB Unassigned 1 " "Info: 4: + IC(1.367 ns) + CELL(0.292 ns) = 3.776 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'address_tmp~71'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.659 ns" { address_tmp~70 address_tmp~71 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 4.429 ns address_tmp~72 5 COMB Unassigned 1 " "Info: 5: + IC(0.361 ns) + CELL(0.292 ns) = 4.429 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'address_tmp~72'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { address_tmp~71 address_tmp~72 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.607 ns) 5.247 ns address_tmp\[0\] 6 REG Unassigned 2 " "Info: 6: + IC(0.211 ns) + CELL(0.607 ns) = 5.247 ns; Loc. = Unassigned; Fanout = 2; REG Node = 'address_tmp\[0\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.818 ns" { address_tmp~72 address_tmp[0] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.747 ns ( 33.30 % ) " "Info: Total cell delay = 1.747 ns ( 33.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 66.70 % ) " "Info: Total interconnect delay = 3.500 ns ( 66.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { count[5] Equal2~4 address_tmp~70 address_tmp~71 address_tmp~72 address_tmp[0] } "NODE_NAME" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { count[5] Equal2~4 address_tmp~70 address_tmp~71 address_tmp~72 address_tmp[0] } "NODE_NAME" } }  } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.247 ns register register " "Info: Estimated most critical path is register to register delay of 5.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[5\] 1 REG LAB_X30_Y15 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y15; Fanout = 8; REG Node = 'count\[5\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[5] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.114 ns) 0.782 ns Equal2~4 2 COMB LAB_X30_Y15 7 " "Info: 2: + IC(0.668 ns) + CELL(0.114 ns) = 0.782 ns; Loc. = LAB_X30_Y15; Fanout = 7; COMB Node = 'Equal2~4'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.782 ns" { count[5] Equal2~4 } "NODE_NAME" } } { "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/90/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.442 ns) 2.117 ns address_tmp~70 3 COMB LAB_X29_Y16 1 " "Info: 3: + IC(0.893 ns) + CELL(0.442 ns) = 2.117 ns; Loc. = LAB_X29_Y16; Fanout = 1; COMB Node = 'address_tmp~70'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { Equal2~4 address_tmp~70 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.292 ns) 3.776 ns address_tmp~71 4 COMB LAB_X31_Y15 1 " "Info: 4: + IC(1.367 ns) + CELL(0.292 ns) = 3.776 ns; Loc. = LAB_X31_Y15; Fanout = 1; COMB Node = 'address_tmp~71'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.659 ns" { address_tmp~70 address_tmp~71 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 4.429 ns address_tmp~72 5 COMB LAB_X31_Y15 1 " "Info: 5: + IC(0.361 ns) + CELL(0.292 ns) = 4.429 ns; Loc. = LAB_X31_Y15; Fanout = 1; COMB Node = 'address_tmp~72'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { address_tmp~71 address_tmp~72 } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.607 ns) 5.247 ns address_tmp\[0\] 6 REG LAB_X31_Y15 2 " "Info: 6: + IC(0.211 ns) + CELL(0.607 ns) = 5.247 ns; Loc. = LAB_X31_Y15; Fanout = 2; REG Node = 'address_tmp\[0\]'" {  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.818 ns" { address_tmp~72 address_tmp[0] } "NODE_NAME" } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.747 ns ( 33.30 % ) " "Info: Total cell delay = 1.747 ns ( 33.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 66.70 % ) " "Info: Total interconnect delay = 3.500 ns ( 66.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { count[5] Equal2~4 address_tmp~70 address_tmp~71 address_tmp~72 address_tmp[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X24_Y11 X35_Y21 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X24_Y11 to location X35_Y21" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[1\] GND " "Info: Pin d\[1\] has GND driving its datain port" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { d[1] } } } { "d:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "d\[1\]" } } } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 66 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d\[5\] GND " "Info: Pin d\[5\] has GND driving its datain port" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { d[5] } } } { "d:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "d\[5\]" } } } } { "da1_test.vhd" "" { Text "D:/da1_test/da1_test.vhd" 66 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/da1_test/da1_test.fit.smsg " "Info: Generated suppressed messages file D:/da1_test/da1_test.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "200 " "Info: Peak virtual memory: 200 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 03 23:25:03 2011 " "Info: Processing ended: Sun Jul 03 23:25:03 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}