da1_test.map.rpt

2013全国电子设计大赛AD9854全部资料，51单片机编程，fpga编程的各种波形发生器

; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                    ;
+----------------------------------+-----------------+-----------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type             ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------------+------------------------------+
; da1_test.vhd                     ; yes             ; Auto-Found VHDL File  ; D:/da1_test/da1_test.vhd     ;
+----------------------------------+-----------------+-----------------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 79    ;
;     -- Combinational with no register       ; 41    ;
;     -- Register only                        ; 16    ;
;     -- Combinational with a register        ; 22    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 33    ;
;     -- 3 input functions                    ; 17    ;
;     -- 2 input functions                    ; 12    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 70    ;
;     -- arithmetic mode                      ; 9     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 38    ;
; Total logic cells in carry chains           ; 11    ;
; I/O pins                                    ; 18    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 39    ;
; Total fan-out                               ; 282   ;
; Average fan-out                             ; 2.91  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |da1_test                  ; 79 (79)     ; 38           ; 0           ; 18   ; 0            ; 41 (41)      ; 16 (16)           ; 22 (22)          ; 11 (11)         ; 0 (0)      ; |da1_test           ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; data_tmp[5]                           ; Merged with data_tmp[1]                ;
; data_tmp[1]                           ; Stuck at GND due to stuck port data_in ;
; d[5]~reg0                             ; Stuck at GND due to stuck port data_in ;
; d[1]~reg0                             ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 4 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                        ;
+---------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal        ; Registers Removed due to This Register ;
+---------------+---------------------------+----------------------------------------+
; data_tmp[1]   ; Stuck at GND              ; d[5]~reg0, d[1]~reg0                   ;
;               ; due to stuck port data_in ;                                        ;
+---------------+---------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 38    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Sun Jul 03 23:24:50 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off da1_test -c da1_test
Warning: Using design file da1_test.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: da1_test-Behavioral
    Info: Found entity 1: da1_test
Info: Elaborating entity "da1_test" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "d[1]" is stuck at GND
    Warning (13410): Pin "d[5]" is stuck at GND
Info: Implemented 97 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 17 output pins
    Info: Implemented 79 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 193 megabytes
    Info: Processing ended: Sun Jul 03 23:24:54 2011
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:04