da1_test.tan.rpt

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; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 9.596 ns   ; a[4]~reg0    ; a[4]    ; clk        ;
; N/A   ; None         ; 9.581 ns   ; d[6]~reg0    ; d[6]    ; clk        ;
; N/A   ; None         ; 9.577 ns   ; d[0]~reg0    ; d[0]    ; clk        ;
; N/A   ; None         ; 9.571 ns   ; a[5]~reg0    ; a[5]    ; clk        ;
; N/A   ; None         ; 9.541 ns   ; d[2]~reg0    ; d[2]    ; clk        ;
; N/A   ; None         ; 9.157 ns   ; d[4]~reg0    ; d[4]    ; clk        ;
; N/A   ; None         ; 9.153 ns   ; io_ud~reg0   ; io_ud   ; clk        ;
; N/A   ; None         ; 8.645 ns   ; a[0]~reg0    ; a[0]    ; clk        ;
; N/A   ; None         ; 7.402 ns   ; d[7]~reg0    ; d[7]    ; clk        ;
; N/A   ; None         ; 7.062 ns   ; a[1]~reg0    ; a[1]    ; clk        ;
; N/A   ; None         ; 6.842 ns   ; a[3]~reg0    ; a[3]    ; clk        ;
; N/A   ; None         ; 6.707 ns   ; d[3]~reg0    ; d[3]    ; clk        ;
; N/A   ; None         ; 6.446 ns   ; a[2]~reg0    ; a[2]    ; clk        ;
; N/A   ; None         ; 6.446 ns   ; mst_rst~reg0 ; mst_rst ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+----------------------------------------------------------+
; tpd                                                      ;
+-------+-------------------+-----------------+------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To  ;
+-------+-------------------+-----------------+------+-----+
; N/A   ; None              ; 5.218 ns        ; clk  ; wrb ;
+-------+-------------------+-----------------+------+-----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Sun Jul 03 23:25:15 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off da1_test -c da1_test --timing_analysis_only
Info: Only one processor detected - disabling parallel compilation
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 172.12 MHz between source register "count[5]" and destination register "address_tmp[5]" (period= 5.81 ns)
    Info: + Longest register to register delay is 5.549 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y15_N4; Fanout = 8; REG Node = 'count[5]'
        Info: 2: + IC(0.533 ns) + CELL(0.442 ns) = 0.975 ns; Loc. = LC_X30_Y15_N7; Fanout = 7; COMB Node = 'Equal2~4'
        Info: 3: + IC(1.587 ns) + CELL(0.292 ns) = 2.854 ns; Loc. = LC_X29_Y16_N7; Fanout = 5; COMB Node = 'Equal3~2'
        Info: 4: + IC(0.440 ns) + CELL(0.590 ns) = 3.884 ns; Loc. = LC_X29_Y16_N9; Fanout = 6; COMB Node = 'address_tmp~65'
        Info: 5: + IC(1.187 ns) + CELL(0.478 ns) = 5.549 ns; Loc. = LC_X32_Y16_N2; Fanout = 2; REG Node = 'address_tmp[5]'
        Info: Total cell delay = 1.802 ns ( 32.47 % )
        Info: Total interconnect delay = 3.747 ns ( 67.53 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y16_N2; Fanout = 2; REG Node = 'address_tmp[5]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "clk" to source register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X30_Y15_N4; Fanout = 8; REG Node = 'count[5]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "a[4]" through register "a[4]~reg0" is 9.596 ns
    Info: + Longest clock path from clock "clk" to source register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y16_N0; Fanout = 1; REG Node = 'a[4]~reg0'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.410 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y16_N0; Fanout = 1; REG Node = 'a[4]~reg0'
        Info: 2: + IC(4.286 ns) + CELL(2.124 ns) = 6.410 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'a[4]'
        Info: Total cell delay = 2.124 ns ( 33.14 % )
        Info: Total interconnect delay = 4.286 ns ( 66.86 % )
Info: Longest tpd from source pin "clk" to destination pin "wrb" is 5.218 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 39; CLK Node = 'clk'
    Info: 2: + IC(1.641 ns) + CELL(2.108 ns) = 5.218 ns; Loc. = PIN_237; Fanout = 0; PIN Node = 'wrb'
    Info: Total cell delay = 3.577 ns ( 68.55 % )
    Info: Total interconnect delay = 1.641 ns ( 31.45 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 134 megabytes
    Info: Processing ended: Sun Jul 03 23:25:17 2011
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01