xtemac_l.h

xilinx trimode mac driver for linux

/** @name Receiver Configuration Word 1 (RXC1)
 *  @{
 */
#define XTE_RXC1_RXRST_MASK     0x80000000   /**< Receiver reset */
#define XTE_RXC1_RXJMBO_MASK    0x40000000   /**< Jumbo frame enable */
#define XTE_RXC1_RXFCS_MASK     0x20000000   /**< FCS not stripped */
#define XTE_RXC1_RXEN_MASK      0x10000000   /**< Receiver enable */
#define XTE_RXC1_RXVLAN_MASK    0x08000000   /**< VLAN enable */
#define XTE_RXC1_RXHD_MASK      0x04000000   /**< Half duplex */
#define XTE_RXC1_RXLT_MASK      0x02000000   /**< Length/type check disable */
#define XTE_RXC1_ERXC1_MASK     0x0000FFFF   /**< Pause frame source address
                                                  bits [47:32]. Bits [31:0]
                                                  are stored in register
                                                  ERXC0 */
/*@}*/


/** @name Transmitter Configuration (TXC)
 *  @{
 */
#define XTE_TXC_TXRST_MASK      0x80000000   /**< Transmitter reset */
#define XTE_TXC_TXJMBO_MASK     0x40000000   /**< Jumbo frame enable */
#define XTE_TXC_TXFCS_MASK      0x20000000   /**< Generate FCS */
#define XTE_TXC_TXEN_MASK       0x10000000   /**< Transmitter enable */
#define XTE_TXC_TXVLAN_MASK     0x08000000   /**< VLAN enable */
#define XTE_TXC_TXHD_MASK       0x04000000   /**< Half duplex */
#define XTE_TXC_TXIFG_MASK      0x02000000   /**< IFG adjust enable */
/*@}*/


/** @name Flow Control Configuration (FCC)
 *  @{
 */
#define XTE_FCC_RXFLO_MASK      0x20000000   /**< Rx flow control enable */
#define XTE_FCC_TXFLO_MASK      0x40000000   /**< Tx flow control enable */
/*@}*/


/** @name EMAC Configuration (EMCFG)
 * @{
 */
#define XTE_EMCFG_LINKSPD_MASK   0xC0000000  /**< Link speed */
#define XTE_EMCFG_RGMII_MASK     0x20000000  /**< RGMII mode enable */
#define XTE_EMCFG_SGMII_MASK     0x10000000  /**< SGMII mode enable */
#define XTE_EMCFG_1000BASEX_MASK 0x08000000  /**< 1000BaseX mode enable */
#define XTE_EMCFG_HOSTEN_MASK    0x04000000  /**< Host interface enable */
#define XTE_EMCFG_TX16BIT        0x02000000  /**< 16 bit Tx client enable */
#define XTE_EMCFG_RX16BIT        0x01000000  /**< 16 bit Rx client enable */

#define XTE_EMCFG_LINKSPD_10     0x00000000   /**< XTE_EMCFG_LINKSPD_MASK for
                                                   10 Mbit */
#define XTE_EMCFG_LINKSPD_100    0x40000000   /**< XTE_EMCFG_LINKSPD_MASK for
                                                   100 Mbit */
#define XTE_EMCFG_LINKSPD_1000   0x80000000   /**< XTE_EMCFG_LINKSPD_MASK for
                                                   1000 Mbit */
/*@}*/


/** @name EMAC RGMII/SGMII Configuration (GMIC)
 * @{
 */
#define XTE_GMIC_RGLINKSPD_MASK    0xC0000000   /**< RGMII link speed */
#define XTE_GMIC_SGLINKSPD_MASK    0x0000000C   /**< SGMII link speed */
#define XTE_GMIC_RGSTATUS_MASK     0x00000002   /**< RGMII link status */
#define XTE_GMIC_RGHALFDUPLEX_MASK 0x00000001   /**< RGMII half duplex */

#define XTE_GMIC_RGLINKSPD_10      0x00000000   /**< XTE_GMIC_RGLINKSPD_MASK
                                                     for 10 Mbit */
#define XTE_GMIC_RGLINKSPD_100     0x40000000   /**< XTE_GMIC_RGLINKSPD_MASK
                                                     for 100 Mbit */
#define XTE_GMIC_RGLINKSPD_1000    0x80000000   /**< XTE_GMIC_RGLINKSPD_MASK
                                                     for 1000 Mbit */
#define XTE_GMIC_SGLINKSPD_10      0x00000000   /**< XTE_SGMIC_RGLINKSPD_MASK
                                                     for 10 Mbit */
#define XTE_GMIC_SGLINKSPD_100     0x00000004   /**< XTE_SGMIC_RGLINKSPD_MASK
                                                     for 100 Mbit */
#define XTE_GMIC_SGLINKSPD_1000    0x00000008   /**< XTE_SGMIC_RGLINKSPD_MASK
                                                     for 1000 Mbit */
/*@}*/


/** @name EMAC Management Configuration (MC)
 * @{
 */
#define XTE_MC_MDIO_MASK       0x00000040   /**< MII management enable */
#define XTE_MC_CLK_DVD_MAX     0x3F         /**< Maximum MDIO divisor */
/*@}*/


/** @name EMAC Unicast Address Register Word 1 (UAW1)
 * @{
 */
#define XTE_UAW1_MASK          0x0000FFFF   /**< Station address bits [47:32]
                                                 Station address bits [31:0]
                                                 are stored in register
                                                 UAW0 */
/*@}*/


/** @name EMAC Multicast Address Register Word 1 (MAW1)
 * @{
 */
#define XTE_MAW1_CAMRNW_MASK   0x00800000   /**< CAM read/write control */
#define XTE_MAW1_CAMADDR_MASK  0x00030000   /**< CAM address mask */
#define XTE_MAW1_MASK          0x0000FFFF   /**< Multicast address bits [47:32]
                                                 Multicast address bits [31:0]
                                                 are stored in register
                                                 MAW0 */
#define XTE_MAW1_CAMMADDR_SHIFT_MASK 16     /**< Number of bits to shift right
                                                 to align with
                                                 XTE_MAW1_CAMADDR_MASK */
/*@}*/


/** @name EMAC Address Filter Mode (AFM)
 * @{
 */
#define XTE_AFM_EPPRM_MASK     0x80000000   /**< Promiscuous mode enable */
/*@}*/


/** @name Checksum offload buffer descriptor extensions
 * @{
 */
/** Byte offset where checksum should begin (16 bit word) */
#define XTE_BD_TX_CSBEGIN_OFFSET  XDMAV3_BD_USR0_OFFSET

/** Offset where checksum should be inserted (16 bit word) */
#define XTE_BD_TX_CSINSERT_OFFSET (XDMAV3_BD_USR0_OFFSET + 2)

/** Checksum offload control for transmit (16 bit word) */
#define XTE_BD_TX_CSCNTRL_OFFSET  XDMAV3_BD_USR1_OFFSET

/** Seed value for checksum calculation (16 bit word) */
#define XTE_BD_TX_CSINIT_OFFSET   (XDMAV3_BD_USR1_OFFSET + 2)

/** Receive frame checksum calculation (16 bit word) */
#define XTE_BD_RX_CSRAW_OFFSET    (XDMAV3_BD_USR5_OFFSET + 2)

/*@}*/

/** @name TX_CSCNTRL bit mask
 * @{
 */
#define XTE_BD_TX_CSCNTRL_CALC_MASK  0x0001  /**< Enable/disable Tx
                                                  checksum */
/*@}*/

/**************************** Type Definitions *******************************/

/***************** Macros (Inline Functions) Definitions *********************/


/****************************************************************************/
/**
*
* Read the given IPIF register.
*
* @param    BaseAddress is the IPIF base address of the device
* @param    RegOffset is the register offset to be read
*
* @return   The 32-bit value of the register
*
* @note
* C-style signature:
*    u32 XTemac_mReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XTemac_mReadReg(BaseAddress, RegOffset) \
    XIo_In32((BaseAddress) + (RegOffset))


/****************************************************************************/
/**
*
* Write the given IPIF register.
*
* @param    BaseAddress is the IPIF base address of the device
* @param    RegOffset is the register offset to be written
* @param    Data is the 32-bit value to write to the register
*
* @return   None.
*
* @note
* C-style signature:
*    void XTemac_mWriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XTemac_mWriteReg(BaseAddress, RegOffset, Data) \
    XIo_Out32((BaseAddress) + (RegOffset), (Data))

/****************************************************************************/
/**
*
* Convert host register offset to a proper DCR or memory mapped offset (DCR
* not currently supported).
*
* @param    HostRegOffset is the relative regster offset to be converted
*
* @return   The correct offset of the register
*
* @note
* C-style signature:
*    u32 XTemac_mHostOffset(u32 RegOffset)
*
*****************************************************************************/
#define XTemac_mHostOffset(HostRegOffset) \
    ((u32)(HostRegOffset) + XTE_HOST_IPIF_OFFSET)

/****************************************************************************/
/**
*
* Read the given host register.
*
* @param    BaseAddress is the base address of the device
* @param    HostRegOffset is the register offset to be read
*
* @return   The 32-bit value of the register
*
* @note
* C-style signature:
*    u32 XTemac_mReadHostReg(u32 BaseAddress, u32 HostRegOffset)
*
*****************************************************************************/
#define XTemac_mReadHostReg(BaseAddress, HostRegOffset) \
    XIo_In32((BaseAddress) + XTemac_mHostOffset(HostRegOffset))


/****************************************************************************/
/**
*
* Write the given host register.
*
* @param    BaseAddress is the base address of the device
* @param    HostRegOffset is the register offset to be written
* @param    Data is the 32-bit value to write to the register
*
* @return   None.
*
* C-style signature:
*    void XTemac_mWriteHostReg(u32 BaseAddress, u32 RegOffset,
*                              u32 Data)
*
*****************************************************************************/
#define XTemac_mWriteHostReg(BaseAddress, HostRegOffset, Data) \
    XIo_Out32((BaseAddress) + XTemac_mHostOffset(HostRegOffset), (Data))


/****************************************************************************/
/**
*
* Set the station address.
*
* @param    BaseAddress is the base address of the device
* @param    AddressPtr is a pointer to a 6-byte MAC address
*
* @return   None.
*
* @note
* C-style signature:
*    u32 XTemac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr)
*
*****************************************************************************/
#define XTemac_mSetMacAddress(BaseAddress, AddressPtr)              \
{                                                                   \
    u32 Reg;                                                    \
    u8* Aptr = (u8*)(AddressPtr);                           \
                                                                    \
    Reg =  Aptr[0] & 0x000000FF;                                    \
    Reg |= Aptr[1] << 8;                                            \
    Reg |= Aptr[2] << 16;                                           \
    Reg |= Aptr[3] << 24;                                           \
    XTemac_mWriteHostReg((BaseAddress), XTE_UAW0_OFFSET, Reg);      \
                                                                    \
    Reg = XTemac_mReadHostReg((BaseAddress), XTE_UAW1_OFFSET);      \
    Reg &= ~XTE_UAW1_MASK;                                          \
    Reg |= Aptr[4] & 0x000000FF;                                    \
    Reg |= Aptr[5] << 8;                                            \
    XTemac_mWriteHostReg((BaseAddress), XTE_UAW1_OFFSET, Reg);      \
}


/****************************************************************************/
/**
*
* Check to see if the transmission is complete.
*
* @param    BaseAddress is the base address of the device
*
* @return   TRUE if it is done, or FALSE if it is not.
*
* @note
* C-style signature:
*    XBoolean XTemac_mIsTxDone(u32 BaseAddress)
*
*****************************************************************************/
#define XTemac_mIsTxDone(BaseAddress)                                   \
    (((XIo_In32((BaseAddress) + XTE_IPISR_OFFSET) & XTE_IPXR_XMIT_DONE_MASK) == \
      XTE_IPXR_XMIT_DONE_MASK) ? TRUE : FALSE)


/****************************************************************************/
/**
*
* Check to see if the receive FIFO is empty.
*
* @param    BaseAddress is the base address of the device
*
* @return   TRUE if it is empty, or FALSE if it is not.
*
* @note
* C-style signature:
*    XBoolean XTemac_mIsRxEmpty(u32 BaseAddress)
*
*****************************************************************************/
#define XTemac_mIsRxEmpty(BaseAddress)                                  \
    ((XIo_In32((BaseAddress) + XTE_IPISR_OFFSET) & XTE_IPXR_RECV_DONE_MASK) \
     ? FALSE : TRUE)


/****************************************************************************/
/**
*
* Reset the entire core including any attached PHY. Note that there may be a
* settling time required after initiating a reset. See the core spec and the
* PHY datasheet.
*
* @param    BaseAddress is the base address of the device
*
* @return   Nothing
*
* @note
* C-style signature:
*    void XTemac_mReset(u32 BaseAddress)
*
*****************************************************************************/
#define XTemac_mReset(BaseAddress)                                      \
    XIo_Out32((BaseAddress) + XTE_DSR_OFFSET, XTE_DSR_RESET_MASK)


/************************** Function Prototypes ******************************/

void XTemac_Enable(u32 BaseAddress);
void XTemac_Disable(u32 BaseAddress);
int  XTemac_SendFrame(u32 BaseAddress, void *FramePtr, int Size);
int  XTemac_RecvFrame(u32 BaseAddress, void *FramePtr);

#ifdef __cplusplus
  }
#endif

#endif  /* end of protection macro */