xtemac_l.h

xilinx trimode mac driver for linux

/* $Id: */
/******************************************************************************
*
*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
*       FOR A PARTICULAR PURPOSE.
*
*       (c) Copyright 2004-2006 Xilinx Inc.
*       All rights reserved.
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
*
******************************************************************************/

/*****************************************************************************/
/**
*
* @file xtemac_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the Tri-Mode MAC Ethernet (TEMAC) device.
* High-level driver functions are defined in xtemac.h.
*
* @note
*
* Some registers are not accessible when a HW instance is configured for SGDMA.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date     Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rmm  05/24/04 First release for early access.
* 1.00a rmm  06/01/05 General release
* 1.00b rmm  09/23/05 Added MII interrupt bit definitions, removed IFGP register
*                     and associated bit masks, added MGT register and
*                     associated bit masks, removed DIID register, renamed host
*                     register names to match those in the latest HW spec.
* 2.00a rmm  11/21/05 Modified to match HW 3.00a
* </pre>
*
******************************************************************************/

#ifndef XTEMAC_L_H /* prevent circular inclusions */
#define XTEMAC_L_H /* by using protection macros */

/***************************** Include Files *********************************/

#include "xbasic_types.h"
#include "xio.h"
#include "xdmav3_l.h"

#ifdef __cplusplus
extern "C" {
#endif

/************************** Constant Definitions *****************************/

#define XTE_PLB_BD_ALIGNMENT  4      /**< Minimum buffer descriptor alignment
                                          on the PLB bus */
#define XTE_PLB_BUF_ALIGNMENT 8      /**< Minimum buffer alignment when using
                                          HW options that impose alignment
                                          restrictions on the buffer data on
                                          the PLB bus */

#define XTE_RESET_IPIF_DELAY_US 1    /**< Number of Us to delay after IPIF
                                          reset */
#define XTE_RESET_HARD_DELAY_US 4    /**< Number of Us to delay after hard core
                                          reset */

/* Register offset definitions. Unless otherwise noted, register access is
 * 32 bit.
 */

/** @name IPIF interrupt and reset registers
 *  @{
 */
#define XTE_DISR_OFFSET  0x00000000  /**< Device interrupt status */
#define XTE_DIPR_OFFSET  0x00000004  /**< Device interrupt pending */
#define XTE_DIER_OFFSET  0x00000008  /**< Device interrupt enable */
#define XTE_DGIE_OFFSET  0x0000001C  /**< Device global interrupt enable */
#define XTE_IPISR_OFFSET 0x00000020  /**< IP interrupt status */
#define XTE_IPIER_OFFSET 0x00000028  /**< IP interrupt enable */
#define XTE_DSR_OFFSET   0x00000040  /**< Device software reset (write) */
#define XTE_MIR_OFFSET   0x00000040  /**< Device software reset (read) */
/*@}*/


/** @name IPIF transmit and receive packet fifo base offsets
 *        Individual registers and bit definitions are defined in
 *        xpacket_fifo_l_v2_00_a.h. This register group is not accessible if
 *        the device instance is configured for SGDMA.
 *  @{
 */
#define XTE_PFIFO_TXREG_OFFSET   0x00002000  /**< Packet FIFO Tx channel */
#define XTE_PFIFO_RXREG_OFFSET   0x00002010  /**< Packet FIFO Rx channel */
/*@}*/


/** @name IPIF transmit and receive packet fifo data offsets. This register
 *        group is not accessible if the device instance is configured for
 *        SGDMA.
 *  @{
 */
#define XTE_PFIFO_TXDATA_OFFSET  0x00002100  /**< IPIF Tx packet fifo port */
#define XTE_PFIFO_RXDATA_OFFSET  0x00002200  /**< IPIF Rx packet fifo port */
/*@}*/


/** @name IPIF transmit and recieve DMA offsets
 *        Individual registers and bit definitions are defined in xdmav3.h.
 *        This register group is not accessible if the device instance is
 *        configured for FIFO direct.
 *  @{
 */
#define XTE_DMA_SEND_OFFSET      0x00002300  /**< DMA Tx channel */
#define XTE_DMA_RECV_OFFSET      0x00002340  /**< DMA Rx channel */
/*@}*/


/** @name PLB_TEMAC registers. The TPLR, TSR, RPLR, and RSR are not accessible
 *        when a device instance is configured for SGDMA. LLPS is not accessible
 *        when a device instance is configured for FIFO direct.
 *  @{
 */
#define XTE_CR_OFFSET           0x00001000  /**< Control */
#define XTE_TPLR_OFFSET         0x00001004  /**< Tx packet length (FIFO) */
#define XTE_TSR_OFFSET          0x00001008  /**< Tx status (FIFO) */
#define XTE_RPLR_OFFSET         0x0000100C  /**< Rx packet length (FIFO) */
#define XTE_RSR_OFFSET          0x00001010  /**< Receive status */
#define XTE_TPPR_OFFSET         0x00001014  /**< Tx pause packet */
#define XTE_LLPS_OFFSET         0x00001018  /**< LLINK PFIFO status */
#define XTE_MGTDR_OFFSET        0x000033B0  /**< MII data */
#define XTE_MGTCR_OFFSET        0x000033B4  /**< MII control */
/*@}*/


/** @name HARD_TEMAC Core Registers
 * These are registers defined within the device's hard core located in the
 * processor block. They are accessed with the host interface. These registers
 * are addressed offset by XTE_HOST_IPIF_OFFSET or by the DCR base address
 * if so configured.
 *
 * Access to these registers should go through macros XTemac_mReadHostReg()
 * and XTemac_mWriteHostReg() to guarantee proper access.
 * @{
 */
#define XTE_HOST_IPIF_OFFSET    0x00003000  /**< Offset of host registers when
                                                 memory mapped into IPIF */
#define XTE_RXC0_OFFSET         0x00000200  /**< Rx configuration word 0 */
#define XTE_RXC1_OFFSET         0x00000240  /**< Rx configuration word 1 */
#define XTE_TXC_OFFSET          0x00000280  /**< Tx configuration */
#define XTE_FCC_OFFSET          0x000002C0  /**< Flow control configuration */
#define XTE_EMCFG_OFFSET        0x00000300  /**< EMAC configuration */
#define XTE_GMIC_OFFSET         0x00000320  /**< RGMII/SGMII configuration */
#define XTE_MC_OFFSET           0x00000340  /**< Management configuration */
#define XTE_UAW0_OFFSET         0x00000380  /**< Unicast address word 0 */
#define XTE_UAW1_OFFSET         0x00000384  /**< Unicast address word 1 */
#define XTE_MAW0_OFFSET         0x00000388  /**< Multicast address word 0 */
#define XTE_MAW1_OFFSET         0x0000038C  /**< Multicast address word 1 */
#define XTE_AFM_OFFSET          0x00000390  /**< Promisciuous mode */
/*@}*/


/* Register masks. The following constants define bit locations of various
 * control bits in the registers. Constants are not defined for those registers
 * that have a single bit field representing all 32 bits. For further
 * information on the meaning of the various bit masks, refer to the HW spec.
 */

/** @name Interrupt status bits for top level interrupts
 *  These bits are associated with the XTE_DISR_OFFSET, XTE_DIPR_OFFSET,
 *  and XTE_DIER_OFFSET registers.
 * @{
 */
#define XTE_DXR_SEND_FIFO_MASK          0x00000040 /**< Send FIFO channel */
#define XTE_DXR_RECV_FIFO_MASK          0x00000020 /**< Receive FIFO channel */
#define XTE_DXR_CORE_MASK               0x00000004 /**< Core */
#define XTE_DXR_DPTO_MASK               0x00000002 /**< Data phase timeout */
#define XTE_DXR_TERR_MASK               0x00000001 /**< Transaction error */
/*@}*/

/** @name Interrupt status bits for MAC interrupts
 *  These bits are associated with XTE_IPISR_OFFSET and XTE_IPIER_OFFSET
 *  registers.
 *
 *  @{
 */
#define XTE_IPXR_XMIT_DONE_MASK         0x00000001 /**< Tx complete */
#define XTE_IPXR_RECV_DONE_MASK         0x00000002 /**< Rx complete */
#define XTE_IPXR_AUTO_NEG_MASK          0x00000004 /**< Auto negotiation complete */
#define XTE_IPXR_RECV_REJECT_MASK       0x00000008 /**< Rx packet rejected */
#define XTE_IPXR_XMIT_SFIFO_EMPTY_MASK  0x00000010 /**< Tx status fifo empty */
#define XTE_IPXR_RECV_LFIFO_EMPTY_MASK  0x00000020 /**< Rx length fifo empty */
#define XTE_IPXR_XMIT_LFIFO_FULL_MASK   0x00000040 /**< Tx length fifo full */
#define XTE_IPXR_RECV_LFIFO_OVER_MASK   0x00000080 /**< Rx length fifo overrun
                                                        Note that this signal is
                                                        no longer asserted by HW
                                                        */
#define XTE_IPXR_RECV_LFIFO_UNDER_MASK  0x00000100 /**< Rx length fifo underrun */
#define XTE_IPXR_XMIT_SFIFO_OVER_MASK   0x00000200 /**< Tx status fifo overrun */
#define XTE_IPXR_XMIT_SFIFO_UNDER_MASK  0x00000400 /**< Tx status fifo underrun */
#define XTE_IPXR_XMIT_LFIFO_OVER_MASK   0x00000800 /**< Tx length fifo overrun */
#define XTE_IPXR_XMIT_LFIFO_UNDER_MASK  0x00001000 /**< Tx length fifo underrun */
#define XTE_IPXR_RECV_PFIFO_ABORT_MASK  0x00002000 /**< Rx packet rejected due to
                                                        full packet FIFO */
#define XTE_IPXR_RECV_LFIFO_ABORT_MASK  0x00004000 /**< Rx packet rejected due to
                                                        full length FIFO */
#define XTE_IPXR_MII_PEND_MASK          0x00008000 /**< Mii operation now
                                                        pending */
#define XTE_IPXR_MII_DONE_MASK          0x00010000 /**< Mii operation has
                                                        completed */
#define XTE_IPXR_XMIT_PFIFO_UNDER_MASK  0x00020000 /**< Tx packet FIFO
                                                        underrun */
#define XTE_IPXR_XMIT_DMA_MASK          0x00080000 /**< Rx dma channel */
#define XTE_IPXR_RECV_DMA_MASK          0x00100000 /**< Tx dma channel */
#define XTE_IPXR_RECV_FIFO_LOCK_MASK    0x00200000 /**< Rx FIFO deadlock */
#define XTE_IPXR_XMIT_FIFO_LOCK_MASK    0x00400000 /**< Tx FIFO deadlock */


#define XTE_IPXR_RECV_DROPPED_MASK                                      \
    (XTE_IPXR_RECV_REJECT_MASK |                                        \
     XTE_IPXR_RECV_PFIFO_ABORT_MASK |                                   \
     XTE_IPXR_RECV_LFIFO_ABORT_MASK)    /**< IPXR bits that indicate a dropped
                                             receive frame */

#define XTE_IPXR_XMIT_ERROR_MASK                                        \
    (XTE_IPXR_XMIT_SFIFO_OVER_MASK |                                    \
     XTE_IPXR_XMIT_SFIFO_UNDER_MASK |                                   \
     XTE_IPXR_XMIT_LFIFO_OVER_MASK |                                    \
     XTE_IPXR_XMIT_LFIFO_UNDER_MASK |                                   \
     XTE_IPXR_XMIT_PFIFO_UNDER_MASK)    /**< IPXR bits that indicate transmit
                                             errors */

#define XTE_IPXR_RECV_ERROR_MASK                                        \
    (XTE_IPXR_RECV_DROPPED_MASK |                                       \
     XTE_IPXR_RECV_LFIFO_UNDER_MASK)    /**< IPXR bits that indicate receive
                                             errors */

#define XTE_IPXR_FIFO_FATAL_ERROR_MASK                                  \
    (XTE_IPXR_RECV_FIFO_LOCK_MASK |                                     \
     XTE_IPXR_XMIT_FIFO_LOCK_MASK |                                     \
     XTE_IPXR_XMIT_SFIFO_OVER_MASK |                                    \
     XTE_IPXR_XMIT_SFIFO_UNDER_MASK |                                   \
     XTE_IPXR_XMIT_LFIFO_OVER_MASK |                                    \
     XTE_IPXR_XMIT_LFIFO_UNDER_MASK |                                   \
     XTE_IPXR_XMIT_PFIFO_UNDER_MASK |                                   \
     XTE_IPXR_RECV_LFIFO_UNDER_MASK)    /**< IPXR bits that indicate fatal FIFO
                                             errors. These bits can only be
                                             cleared by a device reset */
/*@}*/


/** @name Software reset register (DSR)
 *  @{
 */
#define XTE_DSR_RESET_MASK      0x0000000A  /**< Write this value to DSR to
                                                 reset entire core */
/*@}*/


/** @name Global interrupt enable register (DGIE)
 *  @{
 */
#define XTE_DGIE_ENABLE_MASK    0x80000000  /**< Write this value to DGIE to
                                                 enable interrupts from this
                                                 device */
/*@}*/

/** @name Control Register (CR)
 *  @{
 */
#define XTE_CR_BCREJ_MASK       0x00000004   /**< Disable broadcast address
                                                  filtering */
#define XTE_CR_MCREJ_MASK       0x00000002   /**< Disable multicast address
                                                  filtering */
#define XTE_CR_HRST_MASK        0x00000001   /**< Reset the hard TEMAC core */
/*@}*/


/** @name Transmit Packet Length Register (TPLR)
 *  @{
 */
#define XTE_TPLR_TXPL_MASK      0x00003FFF   /**< Tx packet length in bytes */
/*@}*/


/** @name Transmit Status Register (TSR)
 *  @{
 */
#define XTE_TSR_TPCF_MASK       0x00000001   /**< Transmit packet complete
                                                  flag */

/*@}*/


/** @name Receive Packet Length Register (RPLR)
 *  @{
 */
#define XTE_RPLR_RXPL_MASK      0x00003FFF   /**< Rx packet length in bytes */
/*@}*/


/** @name Receive Status Register (RSR)
 * @{
 */
#define XTE_RSR_RPCF_MASK       0x00000001   /**< Receive packet complete
                                                  flag */
/*@}*/


/** @name MII Mamagement Data register (MGTDR)
 *  @{
 */
#define XTE_MGTDR_MIID_MASK     0x0000FFFF   /**< MII data */
/*@}*/


/** @name MII Mamagement Control register (MGTCR)
 *  @{
 */
#define XTE_MGTCR_RWN_MASK      0x00000400  /**< Read-not-write,0=read
                                                 1=write */
#define XTE_MGTCR_PHYAD_MASK    0x000003E0  /**< PHY address */
#define XTE_MGTCR_REGAD_MASK    0x0000001F  /**< PHY register address */

#define XTE_MGTCR_PHYAD_SHIFT_MASK       5  /**< Shift bits for PHYAD */
/*@}*/


/** @name Transmit Pause Packet Register (TPPR)
 *  @{
 */
#define XTE_TPPR_TPPD_MASK      0x0000FFFF   /**< Tx pause packet data */
/*@}*/