xtemac.h

xilinx trimode mac driver for linux

 * Callback invoked when frame(s) have been received in interrupt driven FIFO
 * direct mode. To set this callback, invoke XTemac_SetHander() with
 * XTE_HANDLER_FIFORECV in the HandlerType parameter.
 *
 * @param CallBackRef is user data assigned when the callback was set.
 *
 */
typedef void (*XTemac_FifoRecvHandler)(void *CallBackRef);

/**
 * Callback invoked when frame(s) have been sent or received in interrupt
 * driven SGDMA mode. To set the send callback, invoke XTemac_SetHandler()
 * with XTE_HANDLER_SGSEND in the HandlerType parameter. For the receive
 * callback use XTE_HANDLER_SGRECV.
 *
 * @param CallBackRef is user data assigned when the callback was set.
 */
typedef void (*XTemac_SgHandler)(void *CallBackRef);

/**
 * Callback invoked when auto-negotiation interrupt is asserted
 * To set this callback, invoke XTemac_SetHandler() with XTE_HANDLER_ANEG in
 * the HandlerType parameter.
 *
 * @param CallBackRef is user data assigned when the callback was set.
 */
typedef void (*XTemac_AnegHandler)(void *CallBackRef);

/**
 * Callback when an asynchronous error occurs. To set this callback, invoke
 * XTemac_SetHandler() with XTE_HANDLER_ERROR in the HandlerType paramter.
 *
 * @param CallBackRef is user data assigned when the callback was set.
 * @param ErrorClass defines what class of error is being reported
 * @param ErrorWord1 definition varies with ErrorClass
 * @param ErrorWord2 definition varies with ErrorClass
 *
 * The following information lists what each ErrorClass is, the source of the
 * ErrorWords, what they mean, and if the device should be reset should it be
 * reported
 *
 * <b>ErrorClass == XST_FIFO_ERROR</b>
 *
 * This error class means there was a fatal error with one of the device FIFOs.
 * This type of error cannot be cleared. The user should initiate a device reset.
 *
 * ErrorWord1 is defined as a bit mask from XTE_IPXR_FIFO_FATAL_ERROR_MASK
 * that originates from the device's IPISR register.
 *
 * ErrorWord2 is reserved.
 *
 *
 * <b>ErrorClass == XST_PFIFO_DEADLOCK</b>
 *
 * This error class indicates that one of the packet FIFOs is reporting a
 * deadlock condition. This means the FIFO is reporting that it is empty and
 * full at the same time. This condition will occur when data being written
 * exceeds the capacity of the packet FIFO. The device should be reset if this
 * error is reported.
 *
 * Note that this error is reported only if the device is configured for FIFO
 * direct mode. For SGDMA, this error is reported in ErrorClass XST_FIFO_ERROR.
 *
 * If ErrorWord1 = XTE_RECV, then the deadlock occurred in the receive channel.
 * If ErrorWord1 = XTE_SEND, then the deadlock occurred in the send channel.
 *
 * ErrorWord2 is reserved.
 *
 *
 * <b>ErrorClass == XST_IPIF_ERROR</b>
 *
 * This error means that a register read or write caused a bus error within the
 * TEMAC's IPIF. This condition is fatal. The user should initiate a device
 * reset.
 *
 * ErrorWord1 is defined as the contents XTE_DISR_OFFSET register where these
 * errors are reported. Bits XTE_DXR_DPTO_MASK and XTE_DXR_TERR_MASK are
 * relevent in this context.
 *
 * ErrorWord2 is reserved.
 *
 *
 * <b>ErrorClass == XST_DMA_ERROR</b>
 *
 * This error class means there was a problem during a DMA transfer.
 *
 * ErrorWord1 defines which channel caused the error XTE_RECV or XTE_SEND.
 *
 * ErrorWord2 is set to the DMA status register XDMAV3_DMASR_OFFSET.
 * The relevent bits to test are XDMAV3_DMASR_DBE_MASK and XDMAV3_DMASR_DBT_MASK.
 * If either of these bits are set, a reset is recommended.
 *
 *
 * <b>ErrorClass == XST_RECV_ERROR</b>
 *
 * This error class means a packet was dropped.
 *
 * ErrorWord1 is defined as the contents of the device's XTE_IPISR_OFFSET
 * relating to receive errors. If any bit is set in the
 * XTE_IPXR_RECV_DROPPED_MASK then a packet was rejected. Refer to xtemac_l.h
 * for more information on what each bit in this mask means.
 *
 * ErrorWord2 is reserved.
 *
 * No action is typically required when this error occurs.
 *
 * Reporting of this error class can be disabled by clearing the
 * XTE_REPORT_RXERR_OPTION.
 *
 * @note
 * See xtemac_l.h for bitmasks definitions and the device hardware spec for
 * further information on their meaning.
 *
 */
typedef void (*XTemac_ErrorHandler)(void *CallBackRef, XStatus ErrorClass,
                                    u32 ErrorWord1, u32 ErrorWord2);
/*@}*/


/**
 * Statistics maintained by the driver
 */
typedef struct
{
    u32 TxDmaErrors;     /**< Number of Tx DMA errors detected */
    u32 TxPktFifoErrors; /**< Number of Tx packet FIFO errors detected */
    u32 TxStatusErrors;  /**< Number of Tx errors derived from XTE_TSR_OFFSET
                                  register */
    u32 RxRejectErrors;  /**< Number of frames discarded due to errors */
    u32 RxDmaErrors;     /**< Number of Rx DMA errors detected */
    u32 RxPktFifoErrors; /**< Number of Rx packet FIFO errors detected */

    u32 FifoErrors;      /**< Number of length/status FIFO errors detected */
    u32 IpifErrors;      /**< Number of IPIF transaction and data phase errors
                                  detected */
    u32 Interrupts;      /**< Number of interrupts serviced */
} XTemac_SoftStats;


/**
 * This typedef contains configuration information for a device.
 */
typedef struct
{
    u16  DeviceId;      /**< Unique ID  of device */
    u32  BaseAddress;   /**< Physical base address of IPIF registers */
    u32  RxPktFifoDepth;/**< Depth of receive packet FIFO in bits */
    u32  TxPktFifoDepth;/**< Depth of transmit packet FIFO in bits */
    u16  MacFifoDepth;  /**< Depth of the status/length FIFOs in entries */
    u8   IpIfDmaConfig; /**< IPIF/DMA hardware configuration */
    u8   TxDre;         /**< Has data realignment engine on Tx channel */
    u8   RxDre;         /**< Has data realignment engine on Rx channel */
    u8   TxCsum;        /**< Has checksum offload on Tx channel */
    u8   RxCsum;        /**< Has checksum offload on Tx channel */
    u8   PhyType;       /**< Which type of PHY interface is used (MII,
                                 GMII, RGMII, ect. */
} XTemac_Config;


/* This type encapsulates a packet FIFO channel and support attributes to
 * allow unaligned data transfers.
 */
typedef struct XTemac_PacketFifo {
    u32          Hold[2];   /* Holding register */
    unsigned         ByteIndex; /* Holding register index */
    unsigned         Width;     /* Width of packet FIFO's keyhole data port in
                                   bytes */
    XPacketFifoV200a Fifo;      /* Packet FIFO channel */
                                /* Function used to transfer data between
                                   FIFO and a buffer */
    XStatus          (*XferFn)(struct XTemac_PacketFifo *Fptr, void *BufPtr,
                               u32 ByteCount, int Eop);
} XTemac_PacketFifo;


/**
 * The XTemac driver instance data. The user is required to allocate a
 * structure of this type for every TEMAC device in the system. A pointer
 * to a structure of this type is then passed to the driver API functions.
 */
typedef struct XTemac
{
    u32  BaseAddress;        /* Base address of IPIF register set */
    u32  IsStarted;          /* Device is currently started */
    u32  IsReady;            /* Device is initialized and ready */
    u32  Options;            /* Current options word */
    u32  Flags;              /* Internal driver flags */
    XTemac_Config Config;        /* HW configuration */

    /* Packet FIFO channels */
    XTemac_PacketFifo RecvFifo;   /* Receive channel */
    XTemac_PacketFifo SendFifo;   /* Transmit channel */

    /* DMA channels */
    XDmaV3 RecvDma;               /* Receive channel */
    XDmaV3 SendDma;               /* Transmit channel */

    /* Callbacks for FIFO direct modes */
    XTemac_FifoRecvHandler FifoRecvHandler;
    XTemac_FifoSendHandler FifoSendHandler;
    void *FifoRecvRef;
    void *FifoSendRef;

    /* Callbacks for SG DMA mode */
    XTemac_SgHandler SgRecvHandler;
    XTemac_SgHandler SgSendHandler;
    void *SgRecvRef;
    void *SgSendRef;

    /* Auto negotiation callback */
    XTemac_AnegHandler AnegHandler;
    void *AnegRef;

    /* Error callback */
    XTemac_ErrorHandler ErrorHandler;
    void *ErrorRef;

    /* Driver maintained statistics */
    XTemac_SoftStats Stats;

} XTemac;


/***************** Macros (Inline Functions) Definitions *********************/

/*****************************************************************************/
/**
*
* This macro can be used to determine if the device is in the started or
* stopped state. To be in the started state, the user must have made a
* successful call to XTemac_Start(). To be in the stopped state, XTemac_Stop()
* or one of the XTemac initialize functions must have been called.
*
* @param InstancePtr is a pointer to the XTemac instance to be worked on.
*
* @return
*
* Boolean TRUE if the device has been started, FALSE otherwise
*
* @note
*
* Signature: u32 XTemac_mIsStarted(XTemac *InstancePtr)
*
******************************************************************************/
#define XTemac_mIsStarted(InstancePtr) \
    (((InstancePtr)->IsStarted == XCOMPONENT_IS_STARTED) ? TRUE : FALSE)

/*****************************************************************************/
/**
*
* This macro determines if the device thinks it has received a frame. This
* function is useful if the device is operating in FIFO direct interrupt driven
* mode. For polled mode, use XTemac_FifoQueryRecvStatus().
*
* @param InstancePtr is a pointer to the XTemac instance to be worked on.
*
* @return
*
* Boolean TRUE if the device interrupt status register reports that a frame
* status and length is available. FALSE otherwise.
*
* @note
*
* Signature: u32 XTemac_mIsRecvFrame(XTemac *InstancePtr)
*
******************************************************************************/
#define XTemac_mIsRecvFrame(InstancePtr)                            \
    ((XTemac_mReadReg((InstancePtr)->BaseAddress, XTE_IPISR_OFFSET) \
      & XTE_IPXR_RECV_DONE_MASK) ? TRUE : FALSE)

/*****************************************************************************/
/**
*
* This macro determines if the device thinks it has dropped a receive frame.
*
* @param InstancePtr is a pointer to the XTemac instance to be worked on.
*
* @return
*
* Boolean TRUE if the device interrupt status register reports that a frame
* has been dropped. FALSE otherwise.
*
* @note
*
* Signature: u32 XTemac_mIsRecvFrameDropped(XTemac *InstancePtr)
*
******************************************************************************/
#define XTemac_mIsRecvFrameDropped(InstancePtr)                     \
    ((XTemac_mReadReg((InstancePtr)->BaseAddress, XTE_IPISR_OFFSET) \
      & XTE_IPXR_RECV_REJECT_MASK) ? TRUE : FALSE)

/*****************************************************************************/
/**
*
* This macro determines if the device is currently configured for
* FIFO direct mode
*
* @param InstancePtr is a pointer to the XTemac instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured for FIFO direct, or FALSE
* if it is not.
*
* @note
*
* Signature: u32 XTemac_mIsFifo(XTemac *InstancePtr)
*
******************************************************************************/
#define XTemac_mIsFifo(InstancePtr) \
    (((InstancePtr)->Config.IpIfDmaConfig == XTE_CFG_NO_DMA) ? TRUE : FALSE)

/*****************************************************************************/
/**
*
* This macro determines if the device is currently configured for
* scatter-gather DMA.
*
* @param InstancePtr is a pointer to the XTemac instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE
* if it is not.
*
* @note
*
* Signature: u32 XTemac_mIsSgDma(XTemac *InstancePtr)
*
******************************************************************************/
#define XTemac_mIsSgDma(InstancePtr) \
    (((InstancePtr)->Config.IpIfDmaConfig == XTE_CFG_DMA_SG) ? TRUE : FALSE)

/*****************************************************************************/
/**
*
* This macro determines if the device is configured with the Data Realignment
* Engine (DRE) on the receive channel
*
* @param InstancePtr is a pointer to the XTemac instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with DRE, or FALSE otherwise.
*
* @note
*
* Signature: u32 XTemac_mIsRxDre(XTemac *InstancePtr)
*
******************************************************************************/
#define XTemac_mIsRxDre(InstancePtr) (((InstancePtr)->Config.RxDre) ?  \
                                      TRUE : FALSE)

/*****************************************************************************/
/**
*
* This macro determines if the device is configured with the Data Realignment
* Engine (DRE) on the transmit channel
*
* @param InstancePtr is a pointer to the XTemac instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with DRE, or FALSE otherwise.
*