szz.syr

VHDL设计的数字时钟

#      LUT4_D                      : 6
#      LUT4_L                      : 6
#      MUXCY                       : 93
#      MUXF5                       : 3
#      VCC                         : 1
#      XORCY                       : 93
# FlipFlops/Latches                : 155
#      FDE                         : 3
#      FDR                         : 104
#      FDRE                        : 36
#      LD                          : 12
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 18
#      IBUF                        : 4
#      OBUF                        : 14
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4 

 Number of Slices:                     191  out of   1920     9%  
 Number of Slice Flip Flops:           155  out of   3840     4%  
 Number of 4 input LUTs:               346  out of   3840     9%  
 Number of bonded IOBs:                 18  out of    141    12%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
inclk                              | BUFGP                  | 99    |
clk:Q                              | NONE                   | 40    |
clk1:Q                             | NONE                   | 4     |
_n0054(_n00541:O)                  | NONE(*)(dout_3)        | 12    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.472ns (Maximum Frequency: 154.512MHz)
   Minimum input arrival time before clock: 11.082ns
   Maximum output required time after clock: 5.835ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'inclk'
Delay:               5.666ns (Levels of Logic = 3)
  Source:            b_28 (FF)
  Destination:       b_31 (FF)
  Source Clock:      inclk rising
  Destination Clock: inclk rising

  Data Path: b_28 to b_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   0.465  b_28 (b_28)
     LUT4:I0->O            1   0.551   0.240  _n002853 (CHOICE537)
     LUT2:I1->O            1   0.551   0.240  _n002854 (CHOICE538)
     LUT4:I2->O           33   0.551   1.322  _n0028164 (_n0028)
     FDR:R                     1.026          b_0
    ----------------------------------------
    Total                      5.666ns (3.399ns logic, 2.267ns route)
                                       (60.0% logic, 40.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk:Q'
Delay:               6.472ns (Levels of Logic = 4)
  Source:            sec1_2 (FF)
  Destination:       min2_1 (FF)
  Source Clock:      clk:Q rising
  Destination Clock: clk:Q rising

  Data Path: sec1_2 to min2_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             6   0.720   0.688  sec1_2 (sec1_2)
     LUT2:I1->O            1   0.551   0.240  Ker5872_SW0 (N9090)
     LUT4:I1->O            8   0.551   0.747  Ker5872 (N5874)
     LUT4_D:I3->LO         1   0.551   0.100  _n00401 (N10469)
     LUT2:I1->O            8   0.551   0.747  _n00391 (_n0039)
     FDRE:R                    1.026          min2_3
    ----------------------------------------
    Total                      6.472ns (3.950ns logic, 2.522ns route)
                                       (61.0% logic, 39.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk1:Q'
Delay:               3.940ns (Levels of Logic = 1)
  Source:            sel_0 (FF)
  Destination:       sel_1 (FF)
  Source Clock:      clk1:Q rising
  Destination Clock: clk1:Q rising

  Data Path: sel_0 to sel_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   0.720   1.066  sel_0 (sel_0)
     LUT3:I1->O            3   0.551   0.577  Ker58131 (N5815)
     FDR:R                     1.026          sel_2
    ----------------------------------------
    Total                      3.940ns (2.297ns logic, 1.643ns route)
                                       (58.3% logic, 41.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk:Q'
Offset:              6.916ns (Levels of Logic = 4)
  Source:            md1 (PAD)
  Destination:       hou1_3 (FF)
  Destination Clock: clk:Q rising

  Data Path: md1 to hou1_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            49   1.930   1.338  md1_IBUF (md1_IBUF)
     LUT3:I2->O            1   0.551   0.240  Ker57591_SW0 (N10277)
     LUT4_D:I0->LO         1   0.551   0.100  _n00371 (N10471)
     LUT3:I0->O            4   0.551   0.629  _n0034_SW115 (_n0034)
     FDRE:R                    1.026          hou1_0
    ----------------------------------------
    Total                      6.916ns (4.609ns logic, 2.307ns route)
                                       (66.6% logic, 33.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00541:O'
Offset:              11.082ns (Levels of Logic = 10)
  Source:            md1 (PAD)
  Destination:       dout_3 (LATCH)
  Destination Clock: _n00541:O falling

  Data Path: md1 to dout_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            49   1.930   1.338  md1_IBUF (md1_IBUF)
     LUT3:I0->O            8   0.551   0.747  Mmux_m2_Result<2>1 (m2<2>)
     LUT4:I0->O            1   0.551   0.240  _n0052<0>319_SW0 (N10424)
     LUT4:I0->O            1   0.551   0.240  _n0052<0>319 (CHOICE416)
     LUT4:I0->O            1   0.551   0.240  _n0052<0>350_SW0 (N10317)
     LUT4:I3->O            1   0.551   0.240  _n0052<0>350 (CHOICE419)
     LUT4:I0->O            1   0.551   0.240  _n0052<0>572 (CHOICE469)
     LUT2:I1->O            2   0.551   0.465  _n0052<0>584 (_n0052<0>)
     LUT4:I3->O            1   0.551   0.240  _n0052<3>9 (CHOICE22)
     LUT2:I0->O            1   0.551   0.000  _n0052<3>29 (_n0052<3>)
     LD:D                      0.203          dout_3
    ----------------------------------------
    Total                     11.082ns (7.092ns logic, 3.990ns route)
                                       (64.0% logic, 36.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1:Q'
Offset:              5.835ns (Levels of Logic = 1)
  Source:            speak (FF)
  Destination:       speak (PAD)
  Source Clock:      clk1:Q rising

  Data Path: speak to speak
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.240  speak (speak_OBUF)
     OBUF:I->O                 4.875          speak_OBUF (speak)
    ----------------------------------------
    Total                      5.835ns (5.595ns logic, 0.240ns route)
                                       (95.9% logic, 4.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00541:O'
Offset:              5.748ns (Levels of Logic = 1)
  Source:            selout_3 (LATCH)
  Destination:       selout<3> (PAD)
  Source Clock:      _n00541:O falling

  Data Path: selout_3 to selout<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.633   0.240  selout_3 (selout_3)
     OBUF:I->O                 4.875          selout_3_OBUF (selout<3>)
    ----------------------------------------
    Total                      5.748ns (5.508ns logic, 0.240ns route)
                                       (95.8% logic, 4.2% route)

=========================================================================
CPU : 10.05 / 11.06 s | Elapsed : 10.00 / 11.00 s
 
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Total memory usage is 73740 kilobytes