szz.syr

VHDL设计的数字时钟

Release 6.3i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: szz.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : szz.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : szz
Output Format                      : NGC
Target Device                      : xc3s200-4-pq208

---- Source Options
Top Module Name                    : szz
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : szz.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/Xilinx/bin/200404015010成功/wangyicheng.vhd in Library work.
Entity <szz> (Architecture <one>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <szz> (Architecture <one>).
WARNING:Xst:819 - D:/Xilinx/bin/200404015010成功/wangyicheng.vhd line 419: The following signals are missing in the process sensitivity list:
   md3, h1, h2, m1, m2, s1, s2.
Entity <szz> analyzed. Unit <szz> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <szz>.
    Related source file is D:/Xilinx/bin/200404015010成功/wangyicheng.vhd.
WARNING:Xst:737 - Found 4-bit latch for signal <selout>.
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
    Found 1-bit register for signal <speak>.
    Found 4-bit comparator equal for signal <$n0133> created at line 403.
    Found 4-bit comparator equal for signal <$n0134> created at line 403.
    Found 4-bit comparator equal for signal <$n0135> created at line 403.
    Found 4-bit comparator equal for signal <$n0136> created at line 403.
    Found 32-bit up counter for signal <a>.
    Found 32-bit up counter for signal <b>.
    Found 32-bit up counter for signal <c>.
    Found 1-bit register for signal <clk>.
    Found 1-bit register for signal <clk1>.
    Found 1-bit register for signal <clk2>.
    Found 1-bit register for signal <clk3>.
    Found 32-bit up counter for signal <d>.
    Found 4-bit up counter for signal <hou1>.
    Found 4-bit up counter for signal <hou2>.
    Found 4-bit up counter for signal <min1>.
    Found 4-bit up counter for signal <min2>.
    Found 4-bit up counter for signal <sec1>.
    Found 4-bit up counter for signal <sec2>.
    Found 3-bit up counter for signal <sel>.
    Found 4-bit up counter for signal <seth1>.
    Found 4-bit up counter for signal <seth2>.
    Found 4-bit up counter for signal <setm1>.
    Found 4-bit up counter for signal <setm2>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  15 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  16 Multiplexer(s).
Unit <szz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 14
 32-bit up counter                 : 3
 4-bit up counter                  : 10
 3-bit up counter                  : 1
# Registers                        : 4
 1-bit register                    : 4
# Latches                          : 2
 8-bit latch                       : 1
 4-bit latch                       : 1
# Comparators                      : 4
 4-bit comparator equal            : 4
# Multiplexers                     : 4
 4-bit 2-to-1 multiplexer          : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <szz> ...
Loading device for application Xst from file '3s200.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block szz, actual ratio is 11.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : szz.ngr
Top Level Output File Name         : szz
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 19

Macro Statistics :
# Registers                        : 18
#      1-bit register              : 4
#      4-bit register              : 14
# Multiplexers                     : 4
#      2-to-1 multiplexer          : 4
# Comparators                      : 4
#      4-bit comparator equal      : 4

Cell Usage :
# BELS                             : 537
#      GND                         : 1
#      LUT1                        : 110
#      LUT2                        : 33
#      LUT2_D                      : 1
#      LUT3                        : 48
#      LUT3_D                      : 1
#      LUT4                        : 141