szz_map.sdf

VHDL设计的数字时钟

  )
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        (ABSOLUTE
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        (ABSOLUTE
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    (INSTANCE a_16_DXMUX_117)
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        (ABSOLUTE
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      (DELAY
        (ABSOLUTE
          (PORT I0 (591:591:591)(591:591:591))
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          (IOPATH I1 O (0:0:0)(0:0:0))
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        (ABSOLUTE
          (PORT IA (19:19:19)(19:19:19))
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
          (PORT I0 (591:591:591)(591:591:591))
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        (ABSOLUTE
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        (ABSOLUTE
          (IOPATH I O (301:301:301)(301:301:301))
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    (INSTANCE a_18_CYSELF_136)
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        (ABSOLUTE
          (IOPATH I O (0:0:0)(0:0:0))
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        (ABSOLUTE
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        (ABSOLUTE
          (PORT I0 (591:591:591)(591:591:591))
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    (INSTANCE a_18_FASTCARRY_139)
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
          (IOPATH IA O (0:0:0)(0:0:0))
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        (ABSOLUTE
          (PORT IA (25:25:25)(25:25:25))
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          (IOPATH I O (0:0:0)(0:0:0))
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  (CELL (CELLTYPE "X_SFF")
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          (IOPATH CLK O (720:720:720)(720:720:720))
          (IOPATH SET O (720:720:720)(720:720:720))
          (IOPATH RST O (720:720:720)(720:720:720))
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      (TIMINGCHECK
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        (SETUPHOLD (negedge I) (posedge CLK) (81:81:81) (381:381:381))
        (SETUPHOLD (posedge CE) (posedge CLK) (602:602:602) (0:0:0))
        (SETUPHOLD (negedge CE) (posedge CLK) (602:602:602) (0:0:0))
        (PERIOD (posedge CLK) (1514:1514:1514))
        (SETUPHOLD (posedge SSET) (posedge CLK) (990:990:990) (0:0:0))
        (SETUPHOLD (negedge SSET) (posedge CLK) (990:990:990) (0:0:0))
        (SETUPHOLD (posedge SRST) (posedge CLK) (990:990:990) (0:0:0))
        (SETUPHOLD (negedge SRST) (posedge CLK) (990:990:990) (0:0:0))
        (WIDTH (posedge SET) (1725:1725:1725))
        (WIDTH (posedge RST) (1725:1725:1725))
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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        (ABSOLUTE
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      (DELAY
        (ABSOLUTE
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