wang's.ucf

VHDL设计的数字时钟

net md3 loc =p87;
net md2<1> loc =p90;
net md2<0> loc =p93;
net md1 loc =p94;
net selout<3> loc=p97;
net selout<2> loc=p100;
net selout<1> loc=p101;
net selout<0> loc=p106;
net en loc=p108;
net dout<0> loc =p114;
net dout<1> loc =p115;
net dout<2> loc =p117;
net dout<3> loc =p119;
net dout<4> loc =p120;
net dout<5> loc =p113;
net dout<6> loc =p111;
net dout<7> loc =p116;
net speak loc =p162;