reg515a.h

ps2 to ubs bridge sourc for 8051e code

/*--------------------------------------------------------------------------
REG51.H

Header file for generic 80C51 and 80C31 microcontroller.
Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.
--------------------------------------------------------------------------*/

/*  BYTE Register  */
sfr P0       = 0x80;
sfr SP       = 0x81;
sfr DPL      = 0x82;
sfr DPH      = 0x83;
sfr DPL1     = 0x84;
sfr DPH1     = 0x85;
sfr WDTREL   = 0x86;
sfr PCON     = 0x87;
sfr TIM_STA  = 0x88;
sfr TIM_SEL  = 0x89;
sfr TIM_IO   = 0x8A;
sfr TIM_CTL  = 0x8B;
sfr TIM_PRE  = 0x8C;
sfr TIMER    = 0x8D;
sfr ADC_CTL1 = 0x8E;
sfr ADC_CTL2 = 0x8F;

sfr P1       = 0x90;
sfr ADC_IO   = 0x91;
sfr DPS      = 0x92;
sfr P6       = 0x93;
sfr P6D	     = 0x94;
sfr P7       = 0x95;
sfr ADC_D    = 0x97;
sfr S0CON    = 0x98;
sfr S0BUF    = 0x99;
sfr P5       = 0x9A; 
sfr P5D      = 0x9B; 
sfr P5OD     = 0x9C; 
sfr PS2B_CTL = 0x9D; 
sfr PS2B_STA = 0x9E; 
sfr PS2B_D   = 0x9F;

sfr P2       = 0xA0; 
sfr CIR_CTL1 = 0xA4; 
sfr CIR_CTL2 = 0xA5; 
sfr CIR_ADD  = 0xA6; 
sfr CIR_CMD  = 0xA7;
sfr IEN0     = 0xA8; 
sfr IP0      = 0xA9; 
sfr S0RELL   = 0xAA; 

sfr PWM_CTL  = 0xAC; 
sfr PWM_IO   = 0xAD; 
sfr PWM_PRD  = 0xAE; 
sfr PWM_DTY  = 0xAF;

sfr P3       = 0xB0; 
sfr IICS_CTL = 0xB1; 
sfr IICS_ST  = 0xB2; 
sfr IICS_ID  = 0xB3; 
sfr IICS_TD  = 0xB4; 
sfr IICS_RD  = 0xB5; 
sfr IICS_IDM = 0xB6; 
sfr IICM_CTL = 0xB7;
sfr IEN1     = 0xB8; 
sfr IP1      = 0xB9; 
sfr S0RELH   = 0xBA; 
sfr SMBUS_SEL= 0xBB; 
sfr IICM_STA = 0xBC; 
sfr IICM_ID  = 0xBD; 
sfr IICM_TD  = 0xBE; 
sfr IICM_RD  = 0xBF;

sfr SPI_CTL1 = 0xC0; 
sfr SPI_CTL2 = 0xC1; 
sfr SPI_BR   = 0xC2; 
sfr SPI_D    = 0xC3; 
sfr LPC_HCTL = 0xC4; 
sfr PS2A_CTL = 0xC5; 
sfr PS2A_STA = 0xC6; 
sfr PS2A_D   = 0xC7;
sfr P0OD     = 0xC8; 
sfr LPC_CTL0 = 0xC9; 
sfr LPC_CTL1 = 0xCA; 
sfr LPC_CTL2 = 0xCB; 
sfr LPC_IOD  = 0xCC; 
sfr LPC_IO   = 0xCD; 
sfr LPC2AH   = 0xCE; 
sfr LPC2AL   = 0xCF;

sfr PSW      = 0xD0; 
sfr LPC3AH   = 0xD1; 
sfr LPC3AL   = 0xD2; 
sfr LPC_I0   = 0xD3; 
sfr LPC_O0   = 0xD4; 
sfr LPC_S0   = 0xD5; 
sfr LPC_I1   = 0xD6; 
sfr LPC_O1   = 0xD7;
sfr P2OD     = 0xD8; 
sfr LPC_S1   = 0xD9; 
sfr LPC_I2   = 0xDA; 
sfr LPC_O2   = 0xDB; 
sfr LPC_S2   = 0xDC; 
sfr LPC_I3   = 0xDD; 
sfr LPC_O3   = 0xDE; 
sfr LPC_S3   = 0xDF;

sfr ACC      = 0xE0; 
sfr LPC_IRQ0 = 0xE1; 
sfr LPC_IRQ1 = 0xE2; 
sfr LPC_IRQ2 = 0xE3; 
sfr USB_CTL0 = 0xE4; 
sfr USB_CTL1 = 0xE5; 
sfr USB_CTL2 = 0xE6; 
sfr USB_CTL3 = 0xE7;
sfr USB_CTL4 = 0xE8; 
sfr USB_CTL5 = 0xE9; 
sfr USB_STA0 = 0xEA; 
sfr USB_STA1 = 0xEB; 
sfr USB_STA2 = 0xEC; 
sfr USB_EP0  = 0xED; 
sfr USB_EP1  = 0xEE; 
sfr USB_EP2  = 0xEF;

sfr B        = 0xF0; 
sfr KBI_EN   = 0xF1; 
sfr P4       = 0xF2; 
sfr P4D      = 0xF3; 
sfr P4P      = 0xF4; 
sfr P4E      = 0xF5; 
sfr P4F      = 0xF6; 
sfr USB_EPP  = 0xF7;
sfr FLS_CON  = 0xF9; 
sfr FLS_ADDH = 0xF9; 
sfr FLS_ADDL = 0xFA; 
sfr FLS_DIN  = 0xFB; 
sfr P0D      = 0xFC; 
sfr P1D      = 0xFD; 
sfr P2D      = 0xFE; 
sfr CLK_CTL  = 0xFF;
 
/*  BIT Register  */
/*  PSW   */
sbit CY   = 0xD7;
sbit AC   = 0xD6;
sbit F0   = 0xD5;
sbit RS1  = 0xD4;
sbit RS0  = 0xD3;
sbit OV   = 0xD2;
sbit P    = 0xD0;


/*  IEN0   */
sbit EAL  = 0xAF;
sbit WDT  = 0xAE;
sbit EX7  = 0xAD;
sbit ES0  = 0xAC;
sbit ET1  = 0xAB;
sbit EX1  = 0xAA;
sbit ET0  = 0xA9;
sbit EX0  = 0xA8;

/*  IEN1   */
sbit EX8  = 0xBF;
sbit SWDT = 0xBE;
sbit EX6  = 0xBD;
sbit EX5  = 0xBC;
sbit EX4  = 0xBB;
sbit EX3  = 0xBA;
sbit EX2  = 0xB9;
sbit EADC = 0xB8;



/*  SCON  */
sbit SM0  = 0x9F;
sbit SM1  = 0x9E;
sbit SM20 = 0x9D;
sbit REN0 = 0x9C;
sbit TB80 = 0x9B;
sbit RB80 = 0x9A;
sbit TI0  = 0x99;
sbit RI0  = 0x98;