defeight.vhd

来自「设计一个移动无线电话」· VHDL 代码 · 共 17 行

-- The octal D Flip flip module.
library ieee;
use ieee.std_logic_1164.all;
entity DFF8 is
port (D: in STD_LOGIC_VECTOR(0 to 7);
clk: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR(0 to 7));
end DFF8;
architecture DFF8 of DFF8 is
begin
process (clk)
begin
if (clk = '1' and clk'EVENT) then
Q <= D;
end if;
end process;
end DFF8;