📄 mp200_spi.h
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/* * File Name : linux/drivers/char/mp200_spi.h * Function : MP200 SPI interface * Release Version : Ver 1.03 * Release Date : 2006/10/16 * * Copyright (C) NEC Electronics Corporation 2005-2006 * * * This program is free software;you can redistribute it and/or modify it under the terms of * the GNU General Public License as published by Free Softwere Foundation; either version 2 * of License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; * without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * * You should have received a copy of the GNU General Public License along with this program; * If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, * MA 02111-1307, USA. * */#ifndef __DRIVERS_CHAR_MP200_SPI_H#define __DRIVERS_CHAR_MP200_SPI_H#include <asm/arch/spi.h>/* * SPI register */#define SPI_REG(ADDR, OFF) (*(unsigned int volatile *)(ADDR + OFF))#define SPx_MODE(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000000)#define SPx_POL(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000004)#define SPx_CONTROL(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000008)#define SPx_TX_TIM(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x0000000C)#define SPx_TX_DATA(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000010)#define SPx_RX_DATA(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000014)#define SPx_STATUS(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000018)#define SPx_RAW_STATUS(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x0000001C)#define SPx_ENSET(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000020)#define SPx_ENCLR(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000024)#define SPx_FFCLR(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000028)#define SPx_CONTROL2(ADDR) SPI_REG(IO_ADDRESS(ADDR), 0x00000034)#define SPx_TX_DATA_PHYS(ADDR) ((ADDR) + 0x00000010)#define SPx_RX_DATA_PHYS(ADDR) ((ADDR) + 0x00000014)#define SPx_CONTROL_TX_EMP (0x01 << 15)#define SPx_CONTROL_RX_FULL (0x01 << 14)#define SPx_CONTROL_TX_FULL (0x01 << 7)#define SPx_CONTROL_RX_EMP (0x01 << 6)#define SPx_CONTROL_RST (0x01 << 4)#define SPx_CONTROL_WRT (0x01 << 3)#define SPx_CONTROL_RD (0x01 << 2)#define SPx_CONTROL_STOP (0x01 << 1)#define SPx_CONTROL_START (0x01 << 0)#define SPx_STATUS_TX_STOP (0x01 << 6)#define SPx_STATUS_RX_STOP (0x01 << 5)#define SPx_STATUS_TERR (0x01 << 4)#define SPx_STATUS_RDV (0x01 << 3)#define SPx_STATUS_END (0x01 << 2)#define SPx_STATUS_TX_UDR (0x01 << 1)#define SPx_STATUS_RX_OVR (0x01 << 0)#define SPx_STATUS_TX_ALLERR (SPx_STATUS_TX_UDR)#define SPx_STATUS_RX_ALLERR (SPx_STATUS_TERR \ | SPx_STATUS_RX_OVR)#define SPx_STATUS_ALLERR (SPx_STATUS_TX_ALLERR \ | SPx_STATUS_RX_ALLERR)#define SPx_RAW_STATUS_TX_STOP_RAW (0x01 << 6)#define SPx_RAW_STATUS_RX_STOP_RAW (0x01 << 5)#define SPx_RAW_STATUS_TERR_RAW (0x01 << 4)#define SPx_RAW_STATUS_RDV_RAW (0x01 << 3)#define SPx_RAW_STATUS_END_RAW (0x01 << 2)#define SPx_RAW_STATUS_TX_UDR_RAW (0x01 << 1)#define SPx_RAW_STATUS_RX_OVR_RAW (0x01 << 0)#define SPx_RAW_STATUS_TX_ALLERR_RAW (SPx_RAW_STATUS_TX_UDR_RAW)#define SPx_RAW_STATUS_RX_ALLERR_RAW (SPx_RAW_STATUS_TERR_RAW \ | SPx_RAW_STATUS_RX_OVR_RAW)#define SPx_RAW_STATUS_ALLERR_RAW (SPx_RAW_STATUS_TX_ALLERR_RAW \ | SPx_RAW_STATUS_RX_ALLERR_RAW)#define SPx_ENSET_TX_STOP_EN (0x01 << 6)#define SPx_ENSET_RX_STOP_EN (0x01 << 5)#define SPx_ENSET_TERR_EN (0x01 << 4)#define SPx_ENSET_RDV_EN (0x01 << 3)#define SPx_ENSET_END_EN (0x01 << 2)#define SPx_ENSET_TX_UDR_EN (0x01 << 1)#define SPx_ENSET_RX_OVR_EN (0x01 << 0)#define SPx_ENSET_TX_ALLERR_EN (SPx_ENSET_TX_UDR_EN)#define SPx_ENSET_RX_ALLERR_EN (SPx_ENSET_TERR_EN \ | SPx_ENSET_RX_OVR_EN)#define SPx_ENCLR_TX_STOP_MASK (0x01 << 6)#define SPx_ENCLR_RX_STOP_MASK (0x01 << 5)#define SPx_ENCLR_TERR_MASK (0x01 << 4)#define SPx_ENCLR_RDV_MASK (0x01 << 3)#define SPx_ENCLR_END_MASK (0x01 << 2)#define SPx_ENCLR_TX_UDR_MASK (0x01 << 1)#define SPx_ENCLR_RX_OVR_MASK (0x01 << 0)#define SPx_ENCLR_TX_ALLERR_MASK (SPx_ENCLR_TX_UDR_MASK)#define SPx_ENCLR_RX_ALLERR_MASK (SPx_ENCLR_TERR_MASK \ | SPx_ENCLR_RX_OVR_MASK)#define SPx_ENCLR_TX_ALL_MASK (SPx_ENCLR_TX_STOP_MASK \ | SPx_ENCLR_END_MASK \ | SPx_ENCLR_TX_ALLERR_MASK)#define SPx_ENCLR_RX_ALL_MASK (SPx_ENCLR_RX_STOP_MASK \ | SPx_ENCLR_RDV_MASK \ | SPx_ENCLR_RX_ALLERR_MASK)#define SPx_FFCLR_TX_STOP_CLR (0x01 << 6)#define SPx_FFCLR_RX_STOP_CLR (0x01 << 5)#define SPx_FFCLR_TERR_CLR (0x01 << 4)#define SPx_FFCLR_RDV_CLR (0x01 << 3)#define SPx_FFCLR_END_CLR (0x01 << 2)#define SPx_FFCLR_TX_UDR_CLR (0x01 << 1)#define SPx_FFCLR_RX_OVR_CLR (0x01 << 0)#define SPx_FFCLR_ALL_CLR (SPx_FFCLR_TX_STOP_CLR \ | SPx_FFCLR_RX_STOP_CLR \ | SPx_FFCLR_TERR_CLR \ | SPx_FFCLR_RDV_CLR \ | SPx_FFCLR_END_CLR \ | SPx_FFCLR_TX_UDR_CLR \ | SPx_FFCLR_RX_OVR_CLR)#define SPx_CONTROL2_TX_STOP_MODE (0x01 << 9)#define SPx_CONTROL2_RX_STOP_MODE (0x01 << 8)#define SPx_CONTROL2_RX_FIFO_FULL (0x1F << 0)#define SPx_TX_TIM_30WORD (0x00 << 0)#define SPx_TX_TIM_16WORD (0x01 << 0)#define SPx_TX_TIM_8WORD (0x02 << 0)#define SPx_TX_TIM_1WORD (0x03 << 0)/* * device info */#define SPI_NAME "spi"#define SPI_DEV_MAX 2/* * transfer status */#define SPI_UNUSED 0#define SPI_READ 1#define SPI_WRITE 2#define SPI_RW (SPI_READ | SPI_WRITE)/* * other define */#define SPI_BUFSIZE 16384 /* buffer size max [byte] */#define SPI_SMU_PCTL_SPI1 0x1 /* GPIO -> SPI1 */#define SPI_SMU_PCTL_SPI0_SK 0x2 /* SPIO_SK CS0-2 floating */#define SPI_SMU_PCTL_SPI1_SK 0x4 /* SPI1_SK CS0-2 floating */#define SPI_CSW_MASK 0xFFFFF000 /* csw */#define SPI_POL_MASK 0x00000007 /* pol *//* * spi register info */typedef struct { unsigned int volatile *const mode; /* SPx_MODE */ unsigned int volatile *const pol; /* SPx_POL */ unsigned int volatile *const control; /* SPx_CONTROL */ unsigned int volatile *const tx_tim; /* SPx_TX_TIM */ unsigned int volatile *const tx_data; /* SPx_TX_DATA */ unsigned int volatile *const rx_data; /* SPx_RX_DATA */ unsigned int volatile *const status; /* SPx_STATUS */ unsigned int volatile *const raw_status; /* SPx_RAW_STATUS */ unsigned int volatile *const enset; /* SPx_ENSET */ unsigned int volatile *const enclr; /* SPx_ENCLR */ unsigned int volatile *const ffclr; /* SPx_FFCLR */ unsigned int volatile *const control2; /* SPx_CONTROL2 */} spi_regs_t;/* * buffer info */typedef struct { dma_addr_t dma_addr; /* physics address */ unsigned int addr; /* virtual address */ unsigned int size; /* buffer size */} spi_buf_t;/* * transfer info */typedef struct { dma_regs_t *dma_rx_regs; /* dma rx register */ dma_regs_t *dma_tx_regs; /* dma tx register */ int const rx_lch; /* dma rx channel no */ int const tx_lch; /* dma tx channel no */ unsigned int const rx_data; /* rx data transfer address (physics) */ unsigned int const tx_data; /* tx data transfer address (physics) */ unsigned int int_spi; /* int spi no */ unsigned int dma_err; /* dma error status */ unsigned int spi_err; /* spi error status */ unsigned int size; /* transfer size */ unsigned int state; /* transfer status */ wait_queue_head_t wait; /* wait queue */ spinlock_t spinlock; /* spin lock */ spi_buf_t buf; /* buffer info */} spi_trans_t;/* * smu info */typedef struct { unsigned int pclk; /* pclk */ unsigned int sclk; /* sclk */ unsigned int pclk_ctrl; /* pclk ctrl */ unsigned int sclk_ctrl; /* sclk ctrl */ unsigned int reset; /* reset */ unsigned int sclk_div; /* SPIx_SCLK_DIV */ unsigned int pctl_spi; /* PCTL_SPI */} spi_smu_t;/* * spi data info */typedef struct { spi_regs_t *regs; /* spi register info */ spi_trans_t *trans; /* transfer info */ SPI_CONFIG *config; /* spi config info */ spi_smu_t *smu; /* smu info */ struct semaphore sem; /* semaphore */ unsigned int probe; /* probe */} spi_data_t;#endif /* __DRIVERS_CHAR_MP200_SPI_H */⌨️ 快捷键说明
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