spi.h

The attached file is the driver of SPI

/*
 *  File Name	    : linux/include/asm-arm/arch-mp200/spi.h
 *  Function	    : MP200 SPI interface
 *  Release Version : Ver 1.02
 *  Release Date    : 2006/10/16
 *
 *  Copyright (C) NEC Electronics Corporation 2005-2006
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

#ifndef __ASM_ARM_ARCH_MP200_SPI_H
#define __ASM_ARM_ARCH_MP200_SPI_H

/* SPI_CONFIG */
typedef struct {
	unsigned char dev;	/* device */
	unsigned int nbr;	/* bit length (read) */
	unsigned int nbw;	/* bit length (write) */
	unsigned int cs_sel;	/* chip select */
	unsigned int m_s;	/* master/slave */
	unsigned int dma;	/* dma on/off */
	unsigned int pol;	/* cs wait */
	unsigned int sclk;	/* clock */
} SPI_CONFIG;

/* SPI_CONFIG.dev */
#define SPI_DEV_SP0		0
#define SPI_DEV_SP1		1

/* SPI_CONFIG.nbr/nbw (8 to 32) */
#define SPI_NB_8BIT		8
#define SPI_NB_16BIT		16
#define SPI_NB_32BIT		32

/* SPI_CONFIG.cs_sel */
#define SPI_CS_SEL_CS0		(0 << 4)
#define SPI_CS_SEL_CS1		(1 << 4)
#define SPI_CS_SEL_CS2		(2 << 4)
#define SPI_CS_SEL_CS3		(3 << 4)

/* SPI_CONFIG.m_s */
#define SPI_M_S_MASTER		(0 << 1)
#define SPI_M_S_SLAVE		(1 << 1)

/* SPI_CONFIG.dma */
#define SPI_DMA_OFF		(0 << 0)
#define SPI_DMA_ON		(1 << 0)

/* SPI_CONFIG.pol */
#define SPI_CSW_2CLK		(1 << 12)
#define SPI_CSW_4CLK		(3 << 12)
#define SPI_CSW_8CLK		(7 << 12)
#define SPI_CSW_16CLK		(15 << 12)

#define SPI_CK_DLY_OFF		(0 << 2)
#define SPI_CK_DLY_ON		(1 << 2)

#define SPI_CK_POL_POS		(0 << 1)
#define SPI_CK_POL_NEG		(1 << 1)

#define SPI_CS_POL_POS		(0 << 0)
#define SPI_CS_POL_NEG		(1 << 0)

/* SPI_CONFIG.pol : default value */
#define SPI_POL_SP0_CS0		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)
#define SPI_POL_SP0_CS1		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)
#define SPI_POL_SP0_CS2		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)
#define SPI_POL_SP0_CS3		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)

#define SPI_POL_SP1_CS0		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)
#define SPI_POL_SP1_CS1		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)
#define SPI_POL_SP1_CS2		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)
#define SPI_POL_SP1_CS3		\
	(SPI_CSW_8CLK | SPI_CK_DLY_OFF | SPI_CK_POL_NEG | SPI_CS_POL_NEG)

/* SPI_CONFIG.sclk */
#define SPI_SCLK_1500KHZ	1500
#define SPI_SCLK_3MHZ		3000
#define SPI_SCLK_6MHZ		6000
#define SPI_SCLK_12MHZ		12000
#define SPI_SCLK_24MHZ		24000
#define SPI_SCLK_48MHZ		48000

/* flags */
#define SPI_NONBLOCK		1
#define SPI_RW_2CYCLE		2

/* extern */
extern int spi_read(SPI_CONFIG * config, char *buf, unsigned int count,
		    unsigned int flags);
extern int spi_write(SPI_CONFIG * config, char *buf, unsigned int count,
		     unsigned int flags);
extern int spi_cmd_read(SPI_CONFIG * config, char *cmd, char *buf,
			unsigned int flags);

#endif				/* __ASM_ARM_ARCH_MP200_SPI_H */