pm.h

the attached file is the power mangement for MP201

/*
 *  File Name	    : linux/arch/arm/mach-mp200/pm.h
 *  Function	    : pm
 *  Release Version : Ver 1.00
 *  Release Date    : 2006/03/20
 *
 *  Copyright (C) NEC Electronics Corporation 2005-2006
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

#ifndef __ARCH_ARM_MACH_MP200_PM_H
#define __ARCH_ARM_MACH_MP200_PM_H

/* restriction */
/* #define PM_DEEPSLEEP_ECO */

/* warmboot address */
/* asm/arch/mp201_mem.h */

/* PMU registers */
#define PMU_POWER_STAT			(IO_ADDRESS(MP200_PMU_BASE) + 0x0000)
#define PMU_PC				(IO_ADDRESS(MP200_PMU_BASE) + 0x0004)
#define PMU_START			(IO_ADDRESS(MP200_PMU_BASE) + 0x0008)
#define PMU_DDR_RST_WRM 		(IO_ADDRESS(MP200_PMU_BASE) + 0x000c)
#define PMU_MON_ENABLE			(IO_ADDRESS(MP200_PMU_BASE) + 0x0014)
#define PMU_POWER_ON_PC 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0030)
#define PMU_SUBROUTINE0 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0034)
#define PMU_SUBROUTINE1 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0038)
#define PMU_SUBROUTINE2 		(IO_ADDRESS(MP200_PMU_BASE) + 0x003c)
#define PMU_SUBROUTINE3 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0040)
#define PMU_SUBROUTINE4 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0044)
#define PMU_SUBROUTINE5 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0048)
#define PMU_SUBROUTINE6 		(IO_ADDRESS(MP200_PMU_BASE) + 0x004c)
#define PMU_SUBROUTINE7 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0050)
#define PMU_WDT_COUNT_EN		(IO_ADDRESS(MP200_PMU_BASE) + 0x0060)
#define PMU_WDT_COUNT_LMT		(IO_ADDRESS(MP200_PMU_BASE) + 0x0064)
#define PMU_CMD_BUF_RAM 		(IO_ADDRESS(MP200_PMU_BASE) + 0x0800)

/* PMU parameters */
#define PMU_START_SET			0x00000001
#define PMU_WDT_DISABLE 		0x00000000
#define PMU_WDT_MAX_COUNT		0x0003ffff
#define MASK_PMU_DSP_DET		0x00000004
#define MASK_PMU_PE12_DET		0x00000008
#define PMU_CMD_BUF_RAM_SIZE		512	/* (word) */

/* PMU command */
#define IO_PHY_ADDRESS(x)		((((x) & 0x0fc00000) << 4) | ((x) & 0x003fffff))
#define PMU_CMD_REG_WRITE(vadr, data)	0x00000000, IO_PHY_ADDRESS(vadr), (data)
#define PMU_CMD_MWI_WRITE(vadr, data)	0x00010000, IO_PHY_ADDRESS(vadr), (data)
#define PMU_CMD_TIMERWAIT(count)	(0x10000000 | (count))
#define PMU_CMD_INTWAIT()		0x10010000
#define PMU_CMD_L1_STAT_WAIT(wait)	(0x10060000 | (wait))
#define PMU_CMD_LCD_MODE_WAIT(wait)	(0x10080000 | (wait))
#define PMU_CMD_ALWAYSTIMERWAIT(wait)	(0x10090000 | (wait))
#define PMU_CMD_LOCKTIMEWAIT()		0x100a0000
#define PMU_CMD_PMU_END()		0x20000000
#define PMU_CMD_JUMP(offset)		(0x20010000 | (offset))
#define PMU_CMD_AJUMP(pc)		(0x20020000 | (pc))
#define PMU_CMD_RFS()			0x20030000
#define PMU_CMD_SUBROUTINE0_START()	0x20040000
#define PMU_CMD_SUBROUTINE1_START()	0x20080000
#define PMU_CMD_SUBROUTINE2_START()	0x20050000
#define PMU_CMD_SUBROUTINE3_START()	0x20090000
#define PMU_CMD_SUBROUTINE4_START()	0x20060000
#define PMU_CMD_SUBROUTINE5_START()	0x200a0000
#define PMU_CMD_SUBROUTINE6_START()	0x20070000
#define PMU_CMD_SUBROUTINE7_START()	0x200b0000
#define PMU_CMD_WDT_CLEAR()		0x200c0000
#define PMU_CMD_WDT_STOP()		0x200d0000
#define PMU_CMD_WDT_RESTART()		0x200e0000
#define PMU_CMD_NOP()			0xffff0000

/* PMU command parameters */
#define PMU_CMDP_WAIT_FOR_POWER_OFF	0
#define PMU_CMDP_WAIT_FOR_POWER_ON	1
#define PMU_CMDP_WAIT_FOR_LCD_DIRECT	0
#define PMU_CMDP_WAIT_FOR_LCD_NORMAL	1

/* PMU command set function */
#define SET_PMU_CMDS(n, cmds)		mp200_pm_set_pmu_cmds(n, cmds, ARRAY_SIZE(cmds))

/* SMU register */
#define SMU_TEST_CLK_STOP		(IO_ADDRESS(MP200_SMU_S1_BASE) + 0x0100)

/* SMU parameters */
/*  SMU_RESETREQn */
#define MASK_SMU_PE0_RST		0x00000001
#define MASK_SMU_1A_RSM_RST		0x00000269
#define SMU_RST_RESET			0x00000000
#define SMU_RST_UNRESET 		0xffffffff
#define SMU_RSTENA1A_ALL 		0x0007ffff
#define SMU_RSTENA1B_ALL 		0x0000ffff
#define SMU_RSTENADSP_ALL		0x00000003
/*  SMU_WDT_INT_RESET */
#define SMU_TW0_RSTREQ			0x00000100
/* SMU_LPLL_CTRL2, SMU_HPLL_CTRL4 */
#define SMU_PLL_ON			0x00000001
#define SMU_PLL_STANDBY			0x00000000
/*  SMU_OSC */
#define SMU_OSC_ENA_DISABLE		0x00000004 /* 3ms wait */
#define SMU_OSC_ENA_ENABLE		0x00000005 /* 3ms wait */
/*  SMU_AxBCLKCTRLn */
#define SMU_CLKCTRL_NO_AUTO		0x00000000
#define SMU_AHBCLKCTRL0_L1_NO_AUTO	0x00000000 /* LCD off */
#define SMU_AHBCLKCTRL1_L1_NO_AUTO	0x00000000
#define SMU_APBCLKCTRL_L1_NO_AUTO	0x0029038C /* MWI off */
#define SMU_CLKCTRL_L1_NO_AUTO		0x00000001
/*  SMU_GCLKCTRLn */
#define SMU_PE0_CLK_GCK 		0x00000001	/* GCLKCTRLTST */
#define SMU_PE0_CLKENA_GCK		0x01000000	/* GCLKCTRL2 */
#define SMU_MWI_PCLK_GCK		0x10000000
#define SMU_MWI_SCLK_GCK		0x20000000
#define MASK_SMU_PE0_GCK		0x00000003
#define MASK_SMU_PE1_GCK		0x00000003
#define MASK_SMU_PE2_GCK		0x0000000c
#define MASK_SMU_MWI_GCK		0x30000000
#define MASK_SMU_GCK0			0x07FFFFFF
#define MASK_SMU_GCK1			0x3FFFFFFF
#define MASK_SMU_GCK2			0x1F07FFFF
#define MASK_SMU_GCKTST			0x000003FF
#define MASK_SMU_GCK0_L1		0x03FFF0DF /* LCD/USB On */
#define MASK_SMU_GCK1_L1		0x0FCDFFFF
#define MASK_SMU_GCK2_L1		0x1D077D9F
#define SMU_GCK_OFF			0x00000000
#define SMU_GCK_ON			0xffffffff
/* SMU_GIO_INT_CLK_SEL */
#define SMU_GIO_INT_CLK_OSC		0x00000000
#define SMU_GIO_INT_CLK_RTC		0x00000004
/* SMU_RESET_STATE */
#define SMU_RESET_STATE_WARM		0x00000001
#define SMU_RESET_STATE_CLR		0x00000000
/* SMU_PULLCTL_SDR */
#define SMU_PULLCTL_SDR_PDOWN		0x0007ffff
#define SMU_PULLCTL_SDR_PUP		0x00000000
/* SMU_PCTL_SDR */
#define SMU_PCTL_SDR_32BIT		0x00000001
#define SMU_PCTL_SDR_FLOATING		0x00000000
/* MWI_SCLK_DIV */
#define SMU_MWI_DIV_OSC_VAL		0x00000003
/* OSC_CTRL */
#define SMU_OSC_CTRL_SET_VAL		0x00000005 /* 3.0ms MANUAL_SET=0 OSC=ON */
#define SMU_INT_MASK			0x00000001
/* AUTO_FRQ_CHANGE */
#define SMU_PLL_NRM_DIV_MASK		0x0F000000
#define SMU_PLL_DOWN_DIV_MASK		0x000F0000

/*  SMU_AB0_CSnREADCTRL */
#define SMU_AB0_READMODE_SINGLE0	0x00000000
#define SMU_AB0_READMODE_SINGLE1	0x00000001
#define SMU_AB0_READMODE_PAGE		0x00000002
#define SMU_AB0_READMODE_BURST		0x00000003
/*  SMU_AB0_FLASHRCR */
#define SMU_AB0_READ_MODE_ASYNC 	0x00008000
#define SMU_AB0_LATENCY_COUNT_CODE2	0x00001000
#define SMU_AB0_LATENCY_COUNT_CODE3	0x00001800
#define SMU_AB0_LATENCY_COUNT_CODE4	0x00002000
#define SMU_AB0_LATENCY_COUNT_CODE5	0x00002800
#define SMU_AB0_LATENCY_COUNT_CODE6	0x00003000
#define SMU_AB0_LATENCY_COUNT_CODE7	0x00003800
#define SMU_AB0_WAIT_POLARITY_HIGH	0x00000400
#define SMU_AB0_DATA_HOLD_2CLOCK	0x00000200
#define SMU_AB0_WAIT_DELAY_BEFORE	0x00000100
#define SMU_AB0_BURST_SEQUENCE_LINIEAR	0x00000080
#define SMU_AB0_CLOCK_EDGE_RISING	0x00000040
#define SMU_AB0_BURST_WRAP_NO_WRAP	0x00000008
#define SMU_AB0_BURST_LENGTH_4WORD	0x00000001
#define SMU_AB0_BURST_LENGTH_8WORD	0x00000002
#define SMU_AB0_BURST_LENGTH_16WORD	0x00000003
#define SMU_AB0_BURST_LENGTH_CONTINUOUS 0x00000007
#define SMU_AB0_ASYNC_READ_MODE 	( SMU_AB0_READ_MODE_ASYNC	    \
					| SMU_AB0_LATENCY_COUNT_CODE7	    \
					| SMU_AB0_WAIT_POLARITY_HIGH	    \
					| SMU_AB0_DATA_HOLD_2CLOCK	    \
					| SMU_AB0_WAIT_DELAY_BEFORE	    \
					| SMU_AB0_BURST_SEQUENCE_LINIEAR    \
					| SMU_AB0_CLOCK_EDGE_RISING	    \
					| SMU_AB0_BURST_LENGTH_8WORD )
/*  SMU_AB0_FLASHCOMADD */
#define SMU_AB0_VALIDBIT		0x04000000
#define SMU_AB0_RW			0x02000000

/* FIFO register */
#define FIF_WBUFCTRL			(IO_ADDRESS(MP200_FIFO_BASE) + 0x0000)
#define FIF_WBUFSTATE			(IO_ADDRESS(MP200_FIFO_BASE) + 0x0004)
#define FIF_REQPRI			(IO_ADDRESS(MP200_FIFO_BASE) + 0x0008)
#define FIF_FCCTRL			(IO_ADDRESS(MP200_FIFO_BASE) + 0x0100)
#define FIF_FRAMEAADDR			(IO_ADDRESS(MP200_FIFO_BASE) + 0x0104)
#define FIF_FRAMEBADDR			(IO_ADDRESS(MP200_FIFO_BASE) + 0x0108)
#define FIF_FRAMESIZE			(IO_ADDRESS(MP200_FIFO_BASE) + 0x010c)
#define FIF_FCBASEADDR			(IO_ADDRESS(MP200_FIFO_BASE) + 0x0110)
#define FIF_SDRCMDCTRL			(IO_ADDRESS(MP200_FIFO_S1_BASE) + 0x1100)
#define FIF_SDRCONFIGA			(IO_ADDRESS(MP200_FIFO_S1_BASE) + 0x1000)
#define FIF_SDRCONFIGB			(IO_ADDRESS(MP200_FIFO_S1_BASE) + 0x1004)


/* FIFO parameters */
#define FIF_WRITE_THROUGH		0x00000033
#define FIF_WRITE_BUFFER_EMPTY		0x00000011
#define DDR_SELFREFRESH 		0x00000138
#define FIF_CONFIGB_RCSEL_MASK		0x000e0000

/* INTC parameters */
#define MASK_INTC_ALL			0xffffffff
#define GIO0_INT			(1 << (INT_GIO0 - 32))
#define GIO1_INT			(1 << (INT_GIO1 - 32))
#define GIO2_INT			(1 << (INT_GIO2 - 32))
#define GIO3_INT			(1 << (INT_GIO3 - 32))
#define PMU_RESUME_INT			(GIO0_INT | GIO1_INT | GIO2_INT | GIO3_INT)

/* MWI parameters */
#define MWI_ENSET			0x00000001
#define MWI_ENCLR			0x00000001
#define MWI_DATA_LENGTH_8		7
#define MWI_CONT_PWC_A8_D8_TX		( MWI_PACKAGE_MODE				\
					| (MWI_DATA_LENGTH_8 << UWIRE_BIT_DTX_SHIFT)	\
					| ((CS0_EN | CS0) << UWIRE_CS_PWC) )
#define MWI_CONT_PWC_A8_D8_TX_OFF	( MWI_PACKAGE_MODE				\
					| (MWI_DATA_LENGTH_8 << UWIRE_BIT_DTX_SHIFT)	\
					| (CS0_EN << UWIRE_CS_PWC) )


/* AB0 register */
#define AB0_FLASHCOMSET 		(IO_ADDRESS(MP200_ASYNC0_BASE) + 0x0000)

/* AB0 parameters */
#define AB0_CS0 			0x00000001
#define AB0_CS1 			0x00000002
#define AB0_CS2 			0x00000004
#define AB0_CS3 			0x00000008
#define AB0_CS4 			0x00000010
#define AB0_CS5 			0x00000020
#define AB0_SET_MODE			0x00000040

/* flash chip parameters */
#define FLASH_CMD_CONFIGURATION_1ST	0x00000060
#define FLASH_CMD_CONFIGURATION_2ND	0x00000003
#define FLASH0_BASE			MP200_FLASH_BASE
#define FLASH1_BASE			(MP200_FLASH_BASE + FLASH_SIZE)
#define FLASH_SIZE			(MP200_FLASH_SIZE / 2)
#define CHANGE_FLASH_READ_MODE_SIZE	0x100	/* about 256 bytes */

/* default */
#define MP200_LPJ_248MHZ		0x00096fe0 /* T.B.D */
#define MP200_LPJ_164MHZ		0x00063d78 /* T.B.D */
#define MP200_LPJ_124MHZ		0x0004b7f0 /* T.B.D */
#define MP200_LPJ_83MHZ			0x00032847 /* T.B.D */
#define MP200_LPJ_50MHZ			0x0001e6ea /* T.B.D */

#define MP200_LPJ_ECONOMY		0x00007240 /* 12MHz */

#define MP200_PLL_248MHZ		248
#define MP200_PLL_164MHZ		164
#define MP200_PLL_124MHZ		124
#define MP200_PLL_83MHZ			83
#define MP200_PLL_50MHZ			50
#define MP200_PLL_12MHZ			12

#define PM_SLEEP_MODE_NONE		0
/* asm/arch/pm.h */
#define PM_SLEEP_MODE_MAX		PM_SLEEP_MODE_S3

#define PM_INTC_MASK_SAVE_AND_MASK	1
#define PM_INTC_MASK_RESTORE		2

#define MASK_GPIO_KEYSCAN		( (1 << GPIOCORE_INT_PWC_KEY_SCAN_D)	\
					| (1 << GPIOCORE_INT_PWC_KEY_SCAN_P) 	\
					| (1 << GPIOCORE_INT_PWC_KEY_SCAN_E) )
#define MASK_GPIO_RESUME_KEY		(1 << GPIOCORE_INT_PWC_KEY_SCAN_D)

#define MASK_GPIO_KEYDATA		( (1 << GPIOCORE_INT_PWC_KEY_DATA0)	\
					| (1 << GPIOCORE_INT_PWC_KEY_DATA1)	\
					| (1 << GPIOCORE_INT_PWC_KEY_DATA2)	\
					| (1 << GPIOCORE_INT_PWC_KEY_DATA3) )

#define MASK_GPIO_LCDPANEL		( (1 << GPIOCORE_INT_PWC_LCD_OE) \
					| (1 << GPIOCORE_INT_PWC_LED_ON) )

#define MASK_GPIO_RESUME		(1 << GPIOCORE_GPIO_INTOUT)

/* USBWAKE INT */
#define MASK_USBWAKINT			0x10
#define MASK_DETMODE3H_USBWKM		0x03
#define DETMODE3H_USBWKM_RISE		0x01

#define MASK_GPIO_ALL			0xffffffff

/* PWC Parameters */
/* REGA */
#define REGA_VGP1PS_NORMAL		(0x0 << 4)
#define REGA_VGP1PS_PS			(0x1 << 4)
#define REGA_VL0PS_NORMAL		(0x0 << 3)
#define REGA_VL0PS_PS			(0x1 << 3)
#define REGA_DDIOPS_PWM			(0x0 << 2)
#define REGA_DDIOPS_ECO			(0x1 << 2)
#define REGA_PSCNTL0_REGL0ON		(0x0 << 1)
#define REGA_PSCNTL0_DCDCL1ON		(0x1 << 1)
#define REGA_PSCNTDDL1_OFF		(0x0 << 0)
#define REGA_PSCNTDDL1_ON		(0x1 << 0)

#define PWC_REGA_L1_ON			( REGA_VGP1PS_NORMAL \
					| REGA_VL0PS_NORMAL \
					| REGA_DDIOPS_PWM   \
					| REGA_PSCNTL0_DCDCL1ON \
					| REGA_PSCNTDDL1_ON ) /* 0x03 */
#define PWC_REGA_L1_OFF			( REGA_VGP1PS_NORMAL \
					| REGA_VL0PS_NORMAL \
					| REGA_DDIOPS_PWM   \
					| REGA_PSCNTL0_REGL0ON \
					| REGA_PSCNTDDL1_ON ) /* 0x01 */
#define PWC_REGA_L1_OFF_ECO		( REGA_VGP1PS_NORMAL \
					| REGA_VL0PS_NORMAL \
					| REGA_DDIOPS_ECO   \
					| REGA_PSCNTL0_REGL0ON \
					| REGA_PSCNTDDL1_ON ) /* 0x05 */
#define PWC_REGA_L1_OFF_PS		( REGA_VGP1PS_PS \
					| REGA_VL0PS_PS \
					| REGA_DDIOPS_PWM   \
					| REGA_PSCNTL0_REGL0ON \
					| REGA_PSCNTDDL1_ON ) /* 0x19 */
#define PWC_REGA_L1_OFF_ECO_PS		( REGA_VGP1PS_PS \
					| REGA_VL0PS_PS \
					| REGA_DDIOPS_ECO   \
					| REGA_PSCNTL0_REGL0ON \
					| REGA_PSCNTDDL1_ON ) /* 0x1D */

#define PWC_REGA_L0_OFF_ECO_PS		( REGA_VGP1PS_PS \
					| REGA_VL0PS_PS \
					| REGA_DDIOPS_ECO   \
					| REGA_PSCNTL0_REGL0ON \
					| REGA_PSCNTDDL1_OFF ) /* 0x1C */
/* VOUTSET1 */
#define PWC_VOUTSET1_LP07_VAL		0xA2

#ifdef PM_POWERIC_ES_SWITCH
/* REGRSTMSK1 */
#define PWC_REGRSTMSK1_ENABLE		MASK_GPIO_KEYDATA
#define PWC_REGRSTMSK1_DISABLE		0x00
#endif /* PM_POWERIC_ES_SWITCH */

/* WRSTMSK */
#define PWC_WRSTMSK_INTWAK_ENABLE	0x02
#define PWC_WRSTMSK_INTWAK_DISABLE	0x00
/* WRSTCL */
#define PWC_WRSTCL_ARST			0x02
#define PWC_WRSTCL_REGRST		0x01
#define PWC_WRSTCL_CLEAR		(PWC_WRSTCL_ARST | PWC_WRSTCL_REGRST)
/* WAKECONT */
#define WAKECONT_WAKEWAIT_DISABLE	0x01
#define MASK_WAKECONT_WAKEWAIT		0x01

#ifndef __ASSEMBLY__

struct intc_t {
	unsigned int ien;
	unsigned int ids;
	unsigned int imn;
};

struct intc_state {
	unsigned int mask0;
	unsigned int mask1;
};

struct flash_read_param {
	unsigned int flash0_addr;
	unsigned int flash1_addr;
	unsigned int smu_ab0_cs0readctrl;
	unsigned int smu_ab0_cs1readctrl;
	unsigned int smu_ab0_flashrcr;
};

struct pll_param {
  unsigned int const pllsel2;         /* PLLSEL2 */
  unsigned int const auto_frq_change; /* AUTO_FRQ_CHANGE(NRM_DIV,DOWN_DIV) */
  unsigned int const rcsel;           /* FIF_SDRConfigB:RCSel */
};

struct pll_data {
  struct pll_param param;       /* PLLSEL2 */
  unsigned int const mode;      /* PLL mode */
  unsigned int lpj;             /* loops_per_jiffy */
};

/* sleep.S symbole */
extern void warmboot_handler(void);
extern void mp200_cpu_suspend(void);
extern void mp200_change_pll(struct pll_param *);
extern void mp200_change_osc(void);
extern unsigned int warmboot_handler_size;

/* pm_pmu.c symbole */
extern void mp200_pm_set_uwire_clock(void);
extern void mp200_pm_update_lpj(void);
extern void mp200_pm_eco_to_full(unsigned int new);
extern void mp200_pm_full_to_eco(void);
extern unsigned int mp200_pm_get_pll(void);
extern int mp200_pm_set_pll(unsigned int flag);

/* pm.c symbole */
extern int mp200_pm_sleep(unsigned int mode);

#endif				/* __ASSEMBLY__ */

#endif				/* __ARCH_ARM_MACH_MP200_PM_H */