pm.c

the attached file is the power mangement for MP201

/*
 *  File Name	    : linux/arch/arm/mach-mp200/pm.c
 *  Function	    : pm
 *  Release Version : Ver 1.00
 *  Release Date    : 2006/04/05
 *
 *  Copyright (C) NEC Electronics Corporation 2005-2006
 *
 *
 *  This program is free software;you can redistribute it and/or modify it under the terms of
 *  the GNU General Public License as published by Free Softwere Foundation; either version 2
 *  of License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
 *  without even the implied warrnty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along with this program;
 *  If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
 *  MA 02111-1307, USA.
 *
 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/rtc.h>
#include <linux/pm.h>

#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/cacheflush.h>

#include <asm/arch/gpiocore.h>
#include <asm/arch/uwire.h>
#include <asm/arch/smu.h>
#include <asm/arch/mp201_mem.h>
#include <asm/arch/pm.h>

#define PM_POWERIC_ES_SWITCH /* ES1.1 support */

#define PM_DEBUG_REG

#include "uwire.h"
#include "time.h"
#include "pmu.h"
#include "pm.h"

#ifdef PM_POWERIC_ES_SWITCH
#define PWC_LSIVER_ES1_1 0x01
static unsigned int lsiver_old = 0;
#endif /* PM_POWERIC_ES_SWITCH */

static const unsigned int pmu_cmds_s1_suspend[] = {
/* SDR Pull Down */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PDOWN),
/* SDR Floating */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_FLOATING),
/* L1 clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* L1 auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_AHBCLKCTRL0_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_AHBCLKCTRL1_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_APBCLKCTRL_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_L1_NO_AUTO),
/* L1 Reset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, SMU_RSTENA1A_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B_ENA, SMU_RSTENA1B_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP_ENA, SMU_RSTENADSP_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP, SMU_RST_RESET),
/* SET MWI_SCLK_DIV for OSC */
	PMU_CMD_REG_WRITE(SMU_MWI_SCLK_DIV, SMU_MWI_DIV_OSC_VAL),
/* L1 power off*/
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGA << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_OFF << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_OFF),
/* wait L1 power off */
	PMU_CMD_L1_STAT_WAIT(PMU_CMDP_WAIT_FOR_POWER_OFF),
/* Clock RTC */
	PMU_CMD_REG_WRITE(SMU_PLLSEL, SMU_PLLSEL_RTC ),
/* OSC disable */
	PMU_CMD_REG_WRITE(SMU_OSC_CTRL, SMU_OSC_ENA_DISABLE),
/* INTC enable */
	PMU_CMD_REG_WRITE(VA_INTC + MP200_INTC_IT0_IEN1, PMU_RESUME_INT),
/* INTWAIT */
	PMU_CMD_INTWAIT(),
};

static const unsigned int pmu_cmds_s2_suspend[] = {
/* SDR Pull Down */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PDOWN),
/* SDR Floating */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_FLOATING),
/* L1 clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* L1 auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_AHBCLKCTRL0_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_AHBCLKCTRL1_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_APBCLKCTRL_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_L1_NO_AUTO),
/* L1 Reset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, SMU_RSTENA1A_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B_ENA, SMU_RSTENA1B_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP_ENA, SMU_RSTENADSP_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP, SMU_RST_RESET),
/* SET MWI_SCLK_DIV for OSC */
	PMU_CMD_REG_WRITE(SMU_MWI_SCLK_DIV, SMU_MWI_DIV_OSC_VAL),
/* L1 power off*/
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGA << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_OFF << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_OFF),
/* wait L1 power off */
	PMU_CMD_L1_STAT_WAIT(PMU_CMDP_WAIT_FOR_POWER_OFF),
/* Clock RTC */
	PMU_CMD_REG_WRITE(SMU_PLLSEL, SMU_PLLSEL_RTC ),
/* OSC disable */
	PMU_CMD_REG_WRITE(SMU_OSC_CTRL, SMU_OSC_ENA_DISABLE),
/* INTC enable */
	PMU_CMD_REG_WRITE(VA_INTC + MP200_INTC_IT0_IEN1, PMU_RESUME_INT),
/* INTWAIT */
	PMU_CMD_INTWAIT(),
};

static const unsigned int pmu_cmds_s3_suspend[] = {
/* SDR Pull Down */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PDOWN),
/* SDR Floating */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_FLOATING),
/* L1 clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* L1 auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_AHBCLKCTRL0_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_AHBCLKCTRL1_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_APBCLKCTRL_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_L1_NO_AUTO),
/* L1 Reset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, SMU_RSTENA1A_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B_ENA, SMU_RSTENA1B_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP_ENA, SMU_RSTENADSP_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP, SMU_RST_RESET),
/* SET MWI_SCLK_DIV for OSC */
	PMU_CMD_REG_WRITE(SMU_MWI_SCLK_DIV, SMU_MWI_DIV_OSC_VAL ),
/* INTC enable */
	PMU_CMD_REG_WRITE(VA_INTC + MP200_INTC_IT0_IEN1, PMU_RESUME_INT),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
/* WRSTCL ARST/REGRST clear */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_WRSTCL << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_WRSTCL_CLEAR << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
/* WRSTMSK INTWAK enable */
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_WRSTMSK << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_WRSTMSK_INTWAK_ENABLE << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
/* L0 power save mode 1.2V -> 0.7V */
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_VOUTSET1 << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_VOUTSET1_LP07_VAL << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
/* L1 off and L0 power save */
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGA << 24)),
#ifdef PM_DEEPSLEEP_ECO
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_OFF_ECO_PS << 24)),
#else 
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_OFF_PS << 24)),
#endif
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
/* Clock -> RTC */
	PMU_CMD_REG_WRITE(SMU_PLLSEL, SMU_PLLSEL_RTC ),
/* OSC disable */
	PMU_CMD_REG_WRITE(SMU_OSC_CTRL, SMU_OSC_ENA_DISABLE ),
/* INTWAIT */
	PMU_CMD_INTWAIT(),
};

#ifdef PM_POWERIC_ES_SWITCH
static const unsigned int pmu_cmds_s3_suspend_es1_1[] = {
/* SDR Pull Down */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PDOWN),
/* SDR Floating */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_FLOATING),
/* L1 clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2_L1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* L1 auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_AHBCLKCTRL0_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_AHBCLKCTRL1_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_APBCLKCTRL_L1_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_L1_NO_AUTO),
/* L1 Reset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, SMU_RSTENA1A_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B_ENA, SMU_RSTENA1B_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1B, SMU_RST_RESET),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP_ENA, SMU_RSTENADSP_ALL),
	PMU_CMD_REG_WRITE(SMU_RESETREQDSP, SMU_RST_RESET),
/* SET MWI_SCLK_DIV for OSC */
	PMU_CMD_REG_WRITE(SMU_MWI_SCLK_DIV, SMU_MWI_DIV_OSC_VAL ),
/* INTC enable */
	PMU_CMD_REG_WRITE(VA_INTC + MP200_INTC_IT0_IEN1, PMU_RESUME_INT),
/* KEY REGRSTMSK enable */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGRSTMSK1 << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGRSTMSK1_ENABLE << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
/* L0 power save mode and 1.2V -> 0.7V */
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_VOUTSET1 << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_VOUTSET1_LP07_VAL << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGA << 24)),
#ifdef PM_DEEPSLEEP_ECO
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_OFF_ECO_PS << 24)),
#else 
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_OFF_PS << 24)),
#endif
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
/* Clock -> RTC */
	PMU_CMD_REG_WRITE(SMU_PLLSEL, SMU_PLLSEL_RTC ),
/* OSC disable */
	PMU_CMD_REG_WRITE(SMU_OSC_CTRL, SMU_OSC_ENA_DISABLE ),
/* INTWAIT */
	PMU_CMD_INTWAIT(),
};
#endif /* PM_POWERIC_ES_SWITCH */

static const unsigned int pmu_cmds_s1_resume[] = {
/* auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_NO_AUTO),
/* clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* L1 power ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGA << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_ON << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_OFF),
/* SDR 32bit */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_32BIT),
/* SDR Pull Up */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PUP),
/* wait L1_RESET */
	PMU_CMD_L1_STAT_WAIT(PMU_CMDP_WAIT_FOR_POWER_ON),
/* L1(A) unreset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, MASK_SMU_1A_RSM_RST),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_UNRESET),
/* PMU_END */
	PMU_CMD_PMU_END(),
};

static const unsigned int pmu_cmds_s2_resume[] = {
/* auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_NO_AUTO),
/* clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* L1 power ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGA << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGA_L1_ON << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_OFF),
/* SDR 32bit */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_32BIT),
/* SDR Pull Up */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PUP),
/* wait L1_RESET */
	PMU_CMD_L1_STAT_WAIT(PMU_CMDP_WAIT_FOR_POWER_ON),
/* L1(A) unreset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, MASK_SMU_1A_RSM_RST),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_UNRESET),
/* PMU_END */
	PMU_CMD_PMU_END(),
};

static const unsigned int pmu_cmds_s3_resume[] = {
/* auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_NO_AUTO),
/* clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* WRSTMSK INTWAK disable */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_WRSTMSK << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_WRSTMSK_INTWAK_DISABLE << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_OFF),
/* SDR 32bit */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_32BIT),
/* SDR Pull Up */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PUP),
/* wait L1_RESET */
	PMU_CMD_L1_STAT_WAIT(PMU_CMDP_WAIT_FOR_POWER_ON),
/* L1(A) unreset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, MASK_SMU_1A_RSM_RST),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_UNRESET),
/* PMU_END */
	PMU_CMD_PMU_END(),
};

#ifdef PM_POWERIC_ES_SWITCH
static const unsigned int pmu_cmds_s3_resume_es1_1[] = {
/* auto clock control OFF */
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL0, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_AHBCLKCTRL1, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_APBCLKCTRL, SMU_CLKCTRL_NO_AUTO),
	PMU_CMD_REG_WRITE(SMU_CLKCTRL, SMU_CLKCTRL_NO_AUTO),
/* clock gate ON */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0_ENA, MASK_SMU_GCK0),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL0, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_GCK1),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2_ENA, MASK_SMU_GCK2),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL2, SMU_GCK_ON),
/* KEY REGRSTMSK disable */
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_ON),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX),
	PMU_CMD_REG_WRITE(MWI_TXQA, (GPIOCORE_PWC_REGRSTMSK1 << 24)),
	PMU_CMD_REG_WRITE(MWI_TXQ, (PWC_REGRSTMSK1_DISABLE << 24)),
	PMU_CMD_REG_WRITE(MWI_INTENSET, MWI_ENSET),
	PMU_CMD_MWI_WRITE(MWI_START, MWI_START_FLAG),
	PMU_CMD_REG_WRITE(MWI_INTFFCLR, MWI_FFCLR),
	PMU_CMD_REG_WRITE(MWI_CONT, MWI_CONT_PWC_A8_D8_TX_OFF),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1_ENA, MASK_SMU_MWI_GCK),
	PMU_CMD_REG_WRITE(SMU_GCLKCTRL1, SMU_GCK_OFF),
/* SDR 32bit */
	PMU_CMD_REG_WRITE(SMU_PCTL_SDR, SMU_PCTL_SDR_32BIT),
/* SDR Pull Up */
	PMU_CMD_REG_WRITE(SMU_PULLCTL_SDR, SMU_PULLCTL_SDR_PUP),
/* wait L1_RESET */
	PMU_CMD_L1_STAT_WAIT(PMU_CMDP_WAIT_FOR_POWER_ON),
/* L1(A) unreset */
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A_ENA, MASK_SMU_1A_RSM_RST),
	PMU_CMD_REG_WRITE(SMU_RESETREQ1A, SMU_RST_UNRESET),
/* PMU_END */
	PMU_CMD_PMU_END(),
};
#endif /* PM_POWERIC_ES_SWITCH */