velocity_mac.h

VIA千兆网卡芯片VT6122的linux驱动源代码

*/
#define PHYSR0_PHYRST       0x80 
#define PHYSR0_LINKGD       0x40 
#define PHYSR0_FDPX         0x10 
#define PHYSR0_SPDG         0x08 
#define PHYSR0_SPD10        0x04 
#define PHYSR0_RXFLC        0x02 
#define PHYSR0_TXFLC        0x01 

/*
   Bits in the PHYSR1 register
*/
#define PHYSR1_PHYTBI       0x01 

/*
   Bits in the MIICR register
*/
#define MIICR_MAUTO         0x80 
#define MIICR_RCMD          0x40 
#define MIICR_WCMD          0x20 
#define MIICR_MDPM          0x10 
#define MIICR_MOUT          0x08 
#define MIICR_MDO           0x04 
#define MIICR_MDI           0x02 
#define MIICR_MDC           0x01 

/*
   Bits in the MIIADR register
*/
#define MIIADR_SWMPL        0x80 

/*
   Bits in the CFGA register
*/
#define CFGA_PMHCTG         0x08 
#define CFGA_GPIO1PD        0x04 
#define CFGA_ABSHDN         0x02 
#define CFGA_PACPI          0x01 

/*
   Bits in the CFGB register
*/
#define CFGB_GTCKOPT        0x80
#define CFGB_MIIOPT         0x40
#define CFGB_CRSEOPT        0x20
#define CFGB_OFSET          0x10
#define CFGB_CRANDOM        0x08
#define CFGB_CAP            0x04
#define CFGB_MBA            0x02
#define CFGB_BAKOPT         0x01

/*
   Bits in the CFGC register
*/
#define CFGC_EELOAD         0x80 
#define CFGC_BROPT          0x40 
#define CFGC_DLYEN          0x20 
#define CFGC_DTSEL          0x10 
#define CFGC_BTSEL          0x08 
#define CFGC_BPS2           0x04 /* bootrom select[2] */
#define CFGC_BPS1           0x02 /* bootrom select[1] */
#define CFGC_BPS0           0x01 /* bootrom select[0] */

/*
   Bits in the CFGD register
*/
#define CFGD_IODIS          0x80
#define CFGD_MSLVDACEN      0x40
#define CFGD_CFGDACEN       0x20
#define CFGD_PCI64EN        0x10
#define CFGD_HTMRL4         0x08

/*
   Bits in the DCFG1 register (0x7D)
*/
#define DCFG1_XMWI          0x80 
#define DCFG1_XMRM          0x40 
#define DCFG1_XMRL          0x20 
#define DCFG1_PERDIS        0x10 
#define DCFG1_MRDPL         0x08 /* Read-Multiple, VT3216 only */
#define DCFG1_MRWAIT        0x04 
#define DCFG1_MWWAIT        0x02 
#define DCFG1_LATMEN        0x01 

/*
   Bits in the MCFG0 register
*/
#define MCFG_RXARB          0x0080 
#define MCFG_RFT1           0x0020 
#define MCFG_RFT0           0x0010 
#define MCFG_LOWTHOPT       0x0008 
#define MCFG_PQEN           0x0004 
#define MCFG_RTGOPT         0x0002 
#define MCFG_VIDFR          0x0001 

/*
   Bits in the MCFG1 register
*/
#define MCFG_TXARB          0x8000 
#define MCFG_TXQBK1         0x0800 
#define MCFG_TXQBK0         0x0400 
#define MCFG_TXQNOBK        0x0200 
#define MCFG_SNAPOPT        0x0100 

/*
   Bits in the PMCC  register
*/
#define PMCC_DSI            0x80
#define PMCC_D2_DIS         0x40
#define PMCC_D1_DIS         0x20
#define PMCC_D3C_EN         0x10
#define PMCC_D3H_EN         0x08
#define PMCC_D2_EN          0x04
#define PMCC_D1_EN          0x02
#define PMCC_D0_EN          0x01

/*
   Bits in STICKHW
*/
#define STICKHW_SWPTAG      0x10
#define STICKHW_WOLSR       0x08
#define STICKHW_WOLEN       0x04
#define STICKHW_DS1         0x02 /* R/W by software/cfg cycle */
#define STICKHW_DS0         0x01 /* suspend well DS write port */

/*
   Bits in the MIBCR register
*/
#define MIBCR_MIBISTOK      0x80
#define MIBCR_MIBISTGO      0x40
#define MIBCR_MIBINC        0x20
#define MIBCR_MIBHI         0x10
#define MIBCR_MIBFRZ        0x08
#define MIBCR_MIBFLSH       0x04
#define MIBCR_MPTRINI       0x02
#define MIBCR_MIBCLR        0x01

/*
   Bits in the EERSV register
*/
#define EERSV_BOOT_RPL      0x01 /* Boot method selection for VT6110 */

#define EERSV_BOOT_MASK     0x06
#define EERSV_BOOT_INT19    0x00
#define EERSV_BOOT_INT18    0x02
#define EERSV_BOOT_LOCAL    0x04
#define EERSV_BOOT_BEV      0x06

/*
   Bits in BPCMD
*/
#define BPCMD_BPDNE         0x80
#define BPCMD_EBPWR         0x02
#define BPCMD_EBPRD         0x01

/*
   Bits in the EECSR register
*/
#define EECSR_EMBP          0x40 /* eeprom embeded programming */
#define EECSR_RELOAD        0x20 /* eeprom content reload */
#define EECSR_DPM           0x10 /* eeprom direct programming */
#define EECSR_ECS           0x08 /* eeprom CS pin */
#define EECSR_ECK           0x04 /* eeprom CK pin */
#define EECSR_EDI           0x02 /* eeprom DI pin */
#define EECSR_EDO           0x01 /* eeprom DO pin */

/*
   Bits in the EMBCMD register
*/
#define EMBCMD_EDONE        0x80
#define EMBCMD_EWDIS        0x08
#define EMBCMD_EWEN         0x04
#define EMBCMD_EWR          0x02
#define EMBCMD_ERD          0x01

/*
   Bits in TESTCFG register
*/
#define TESTCFG_HBDIS       0x80

/*
   Bits in CHIPGCR register
*/
#define CHIPGCR_FCGMII      0x80
#define CHIPGCR_FCFDX       0x40
#define CHIPGCR_FCRESV      0x20
#define CHIPGCR_FCMODE      0x10
#define CHIPGCR_LPSOPT      0x08
#define CHIPGCR_TM1US       0x04
#define CHIPGCR_TM0US       0x02
#define CHIPGCR_PHYINTEN    0x01

/*
   Bits in WOLCR0
*/
#define WOLCR_MSWOLEN7      0x0080 /* enable pattern match filtering */
#define WOLCR_MSWOLEN6      0x0040
#define WOLCR_MSWOLEN5      0x0020
#define WOLCR_MSWOLEN4      0x0010
#define WOLCR_MSWOLEN3      0x0008
#define WOLCR_MSWOLEN2      0x0004
#define WOLCR_MSWOLEN1      0x0002
#define WOLCR_MSWOLEN0      0x0001
#define WOLCR_ARP_EN        0x0001

/*
   Bits in WOLCR1
*/
#define WOLCR_LINKOFF_EN    0x0800 /* link off detected enable */
#define WOLCR_LINKON_EN     0x0400 /* link on detected enable */
#define WOLCR_MAGIC_EN      0x0200 /* magic packet filter enable */
#define WOLCR_UNICAST_EN    0x0100 /* unicast filter enable */


/*
  Bits in PWCFG
*/
#define PWCFG_PHYPWOPT      0x80 /* internal MII I/F timing */
#define PWCFG_PCISTICK      0x40 /* PCI sticky R/W enable */
#define PWCFG_WOLTYPE       0x20 /* pulse(1) or button (0) */
#define PWCFG_LEGCY_WOL     0x10
#define PWCFG_PMCSR_PME_SR  0x08
#define PWCFG_PMCSR_PME_EN  0x04 /* control by PCISTICK */
#define PWCFG_LEGACY_WOLSR  0x02 /* Legacy WOL_SR shadow */
#define PWCFG_LEGACY_WOLEN  0x01 /* Legacy WOL_EN shadow */

/*
   Bits in WOLCFG
*/
#define WOLCFG_PMEOVR       0x80 /* for legacy use, force PMEEN always */
#define WOLCFG_SAM          0x20 /* accept multicast case reset, default=0 */
#define WOLCFG_SAB          0x10 /* accept broadcast case reset, default=0 */
#define WOLCFG_SMIIACC      0x08 /* ?? */
#define WOLCFG_SGENWH       0x02 
#define WOLCFG_PHYINTEN     0x01 /* 0:PHYINT trigger enable, 1:use internal MII */
                                 /* to report status change */
/*
   Bits in WOLSR1
*/
#define WOLSR_LINKOFF_INT   0x0800
#define WOLSR_LINKON_INT    0x0400
#define WOLSR_MAGIC_INT     0x0200
#define WOLSR_UNICAST_INT   0x0100


/*
   revision id
*/
#define REV_ID_VT3119_A0	0x00
#define REV_ID_VT3119_A1	0x01
#define REV_ID_VT3216_A0	0x10
#define REV_ID_VT3284_A0    0x20    /* [1.18] */

/* wait time within loop */
#define CB_DELAY_LOOP_WAIT  10      /* 10ms */
#define CB_DELAY_MII_STABLE 660     

/* max time out delay time */
#define W_MAX_TIMEOUT       0x0FFFU

typedef
enum __HW_MIBS {
    HW_MIB_ifRxAllPkts=0,
    HW_MIB_ifRxOkPkts,
    HW_MIB_ifTxOkPkts,
    HW_MIB_ifRxErrorPkts,
    HW_MIB_ifRxRuntOkPkt,
    HW_MIB_ifRxRuntErrPkt,
    HW_MIB_ifRx64Pkts,
    HW_MIB_ifTx64Pkts,
    HW_MIB_ifRx65To127Pkts,
    HW_MIB_ifTx65To127Pkts,
    HW_MIB_ifRx128To255Pkts,
    HW_MIB_ifTx128To255Pkts,
    HW_MIB_ifRx256To511Pkts,
    HW_MIB_ifTx256To511Pkts,
    HW_MIB_ifRx512To1023Pkts,
    HW_MIB_ifTx512To1023Pkts,
    HW_MIB_ifRx1024To1518Pkts,
    HW_MIB_ifTx1024To1518Pkts,
    HW_MIB_ifTxEtherCollisions,
    HW_MIB_ifRxPktCRCE,
    HW_MIB_ifRxJumboPkts,
    HW_MIB_ifTxJumboPkts,
    HW_MIB_ifRxMacControlFrames,
    HW_MIB_ifTxMacControlFrames,
    HW_MIB_ifRxPktFAE,
    HW_MIB_ifRxLongOkPkt,
    HW_MIB_ifRxLongPktErrPkt,
    HW_MIB_ifTXSQEErrors,
    HW_MIB_ifRxNobuf,
    HW_MIB_ifRxSymbolErrors,
    HW_MIB_ifInRangeLengthErrors,
    HW_MIB_ifLateCollisions,
    HW_MIB_SIZE
} HW_MIBS, *PHW_MIBS;

typedef enum  _chip_type{
    CHIP_TYPE_VT6110=1,
} CHIP_TYPE, *PCHIP_TYPE;

typedef struct __chip_info_tbl{
    CHIP_TYPE   chip_id;
    char*       name;
    int         io_size;
    int         nTxQueue;
    U32         flags;
} CHIP_INFO, *PCHIP_INFO;

#define mac_hw_mibs_init(hw) {\
    BYTE_REG_BITS_ON(hw, MIBCR_MIBFRZ, MAC_REG_MIBCR);\
    BYTE_REG_BITS_ON(hw, MIBCR_MIBCLR, MAC_REG_MIBCR);\
    do {}\
    while (BYTE_REG_BITS_IS_ON(hw, MIBCR_MIBCLR, MAC_REG_MIBCR));\
    BYTE_REG_BITS_OFF(hw, MIBCR_MIBFRZ, MAC_REG_MIBCR);\
}

#define mac_read_isr(hw)  CSR_READ_4(hw, MAC_REG_ISR)
#define mac_write_isr(hw, x)  CSR_WRITE_4(hw, (x), MAC_REG_ISR)
#define mac_clear_isr(hw) CSR_WRITE_4(hw, 0xffffffffL, MAC_REG_ISR)

#define mac_write_int_mask(mask, hw)  CSR_WRITE_4(hw, (mask), MAC_REG_IMR);
#define mac_disable_int(hw)           CSR_WRITE_4(hw, CR0_GINTMSK1, MAC_REG_CR0_CLR)
#define mac_enable_int(hw)            CSR_WRITE_4(hw, CR0_GINTMSK1, MAC_REG_CR0_SET)

#define mac_hw_mibs_read(hw, adwMIBs) {\
    int i;\
    BYTE_REG_BITS_ON(hw, MIBCR_MPTRINI, MAC_REG_MIBCR);\
    for (i=0;i<HW_MIB_SIZE;i++) {\
        (adwMIBs)[i]=CSR_READ_4(hw, MAC_REG_MIBREAD);\
    }\
}

#define mac_set_dma_length(hw, n) {\
    BYTE_REG_BITS_SET(hw, (n),0x07, MAC_REG_DCFG0);\
}

#define mac_set_rx_thresh(hw, n) {\
    BYTE_REG_BITS_SET(hw, (n),(MCFG_RFT0|MCFG_RFT1), MAC_REG_MCFG0);\
}

#define mac_rx_queue_run(hw) {\
    CSR_WRITE_1(hw, TRDCSR_RUN, MAC_REG_RDCSR_SET);\
}

#define mac_rx_queue_wake(hw) {\
    CSR_WRITE_1(hw, TRDCSR_WAK, MAC_REG_RDCSR_SET);\
}


#define mac_tx_queue_run(hw, n) {\
    CSR_WRITE_2(hw, TRDCSR_RUN<<((n)*4), MAC_REG_TDCSR_SET);\
}

#define mac_tx_queue_wake(hw, n) {\
    CSR_WRITE_2(hw, TRDCSR_WAK<<(n*4), MAC_REG_TDCSR_SET);\
}

#define mac_eeprom_reload(hw) {\
    int i=0;\
    BYTE_REG_BITS_ON(hw, EECSR_RELOAD,MAC_REG_EECSR);\
    do {\
        udelay(10);\
        if (i++>0x1000) {\
            break;\
        }\
    }while (BYTE_REG_BITS_IS_ON(hw, EECSR_RELOAD,MAC_REG_EECSR));\
}

typedef enum {
    VELOCITY_VLAN_ID_CAM=0,
    VELOCITY_MULTICAST_CAM
} VELOCITY_CAM_TYPE, *PVELOCITY_CAM_TYPE;



#endif /* __VELOCITY_MAC_H__ */