basketball_count.v

来自「一个用于篮球比赛30秒计时的程序」· Verilog 代码 · 共 109 行

`timescale 1s/100ms
module BasketbalCount(alarm,outH,outL,stop,load,clk,reset);
	output alarm,outH,outL;
	input stop,load,clk,reset;
	reg alarm;
	reg[3:0] outH,outL;
	reg [4:0] counter;
	reg [2:0] state;
	initial
	   begin
	       alarm=0;
	       counter=0;
	       state=0;
	       outL=4'b0000;
	       outH=4'b0000;
	       end
	always @ (posedge clk or negedge reset)
		begin
			if (!reset)
				begin
					counter <= 0;
					state <= 0;
				end
			else
			case(state)
				0:state <= 1;
				1://counting
				begin
				   if(stop==1)
				      begin
				         state<=3; 
				      end    
				   else if(load==1)
				      begin 
				         state<=4;
				         //counter<=0;
				      end
					else if (counter==30)
						begin
							state <= 2;
							//counter <= 0;
						end
					else if(load==0&stop==0)
						begin
							alarm<=0;
							counter <= counter + 1;
							outL<=outL+1;
							if(outL==4'b1001)
							begin
							   outL<=4'b0000;
							   outH<=outH+1;
							end
						end
			end
				
				2://alarm
				begin
					if (counter ==30&load==0&stop==0)
						begin
							
							counter <= 0;
							alarm<=1;
							state <=1;
						end
					else
						begin
							counter <= counter + 1;
						end
				end
				
				3://stop
				begin
					if (stop==0)
						begin
							state <= 1;
						end
					else
						begin
							counter <= counter;
							outL<=outL;
							outH<=outH;
						end
				end
				
				4://load
				begin
				   if(load==0)
				      state<=1;
				    else
				        begin
				            counter<=0;
				            outL<=0;
				            outH<=0;
				        end 
				end
				
				default:
					begin
						state <= 0;
					end
			endcase
		end


//assign counter  = (state==1)?(counter+1):0;
 endmodule