📄 basketball_test.v
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//------ this design is for test_bench --------////------ `timescale 1s/100ms`define clk_cycle 0.5module Tcontroller_test; reg clk,reset,load,stop; //reg alarm; //reg[3:0] outH,outL; wire alarm; wire[3:0] outH,outL; always #`clk_cycle clk = ~clk; initial begin clk = 0; reset = 1; load=0; stop=0; //alarm=0; //outH=0; //outL=0; #15 load=1; #16 load=0; #47 stop=1; #48 stop=0; endBasketbalCount basketball(alarm,outH,outL,stop,load,clk,reset); endmodule
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