dc_comm.h

使用ISP1362芯片的USB_OTG参考设计源代码比较新的版本

/*
**  WASABI-Hot! version 1.2c    (DeviceController sub-unit)
**
**
**      -- copyright (c) 2001-2004 by Philips Japan, Ltd. -- All rights reserved --
**
**
**      ** This code has been made to check/learn                          ** 
**      **                             the ISP1362/ISP1363 functionalities **
**      ** Release 06-Aug-2004                                             **
**
**     HIGASHIYAMA, Ken 
**      
**		Application Laboratory, Mobile and Connectivity
**      Semiconductors Div, Philips Japan Ltd.
**      [e-mail]
**      [phone] 
**
**
*/

#ifndef _DC_COMMAND_
#define _DC_COMMAND_

#include		"general.h"


//*********************************************************************************************//
//						Device Controller Command Code 
//*********************************************************************************************//

/*				Initialization Commands				*/
#define	W_Ctrl_Out_Config		0x20
#define	W_Ctrl_In_Config		0x21
#define	W_Ep_Config				0x22 -1	// endpoint index to be within [1..14]

#define	R_Control_Out_Config	0x30
#define	R_Control_In_Config		0x31
#define	R_Ep_Config				0x32 -1	// endpoint index to be within [1..14]

#define	W_Device_Address		0xB6
#define	R_Device_Address		0xB7
#define	W_Mode_Register			0xB8
#define	R_Mode_Register			0xB9
#define	W_Hw_Config				0xBA
#define	R_Hw_Config				0xBB

#define	W_Int_Enable			0xC2
#define	R_Int_Enable			0xC3

#define	W_Dma_Config			0xF0
#define	R_Dma_Config			0xF1
#define	W_Dma_Counter			0xF2
#define	R_Dma_Counter			0xF3

#define	Reset_Device			0xF6


/*				Data Flow Commands				*/
//#define	W_Ctrl_Out_Buf		0x00	// illeagal code
#define	W_Ctrl_In_Buf			0x01
#define	W_Ep_Buf				0x02 -1	// endpoint index to be within [1..14]

#define	R_Ctrl_Out_Buf			0x10
//#define	R_Ctrl_In_Buf		0x11	// illeagal code
#define	R_Ep_Buf				0x12 -1	// endpoint index to be within [1..14]

#define	Stall_Ctrl_Out			0x40
#define	Stall_Ctrl_In			0x41
#define	Stall_Ep				0x42 -1	// endpoint index to be within [1..14]

#define	R_Ctrl_Out_Status		0x50
#define	R_Ctrl_In_Status		0x51
#define	R_Ep_Status				0x52 -1	// endpoint index to be within [1..14]

//#define	Valid_Ctrl_Out		0x60	//illeagal code
#define	Valid_Ctrl_In			0x61
#define	Valid_Ep				0x62 -1	// endpoint index to be within [1..14]

#define	Clear_Ctrl_Out			0x70
//#define	Clear_Ctrl_In		0x71	//illeagal code
#define	Clear_Ep				0x72 -1	// endpoint index to be within [1..14]

#define	Unstall_Ctrl_Out		0x80
#define	Unstall_Ctrl_In			0x81
#define	Unstall_Ep				0x82 -1	// endpoint index to be within [1..14]

#define	Chk_Ctrl_Out_Status		0xD0
#define	Chk_Ctrl_In_Status		0xD1
#define	Chk_Ep_Status			0xD2 -1	// endpoint index to be within [1..14]

#define	Ack_Setup				0xF4


/*				General Commands				*/
#define	R_Ctrl_Out_Error		0xA0
#define	R_Ctrl_In_Error			0xA1
#define	R_Ep_Error				0xA2 -1	// endpoint index to be within [1..14]

#define	Unlock_Device			0xB0

#define	W_Scratch				0xB2
#define	R_Scratch				0xB3
#define	R_Frame_Number			0xB4
#define	R_Chip_Id				0xB5

#define	R_Interrupt_Reg			0xC0


//*********************************************************************************************//
//						Bit Definition
//*********************************************************************************************//
//						Endpoint Configuration
#define	FIFOEN			0x80
#define	DIR_IN			0x40
#define	DBLBUF			0x20
#define	FFOISO			0x10
#define	FFOSZ_08		0x00
#define	FFOSZ_16		0x01
#define	FFOSZ_32		0x02
#define	FFOSZ_64		0x03
#define	FFOSZ_I_16		0x00
#define	FFOSZ_I_32		0x01
#define	FFOSZ_I_48		0x02
#define	FFOSZ_I_64		0x03
#define	FFOSZ_I_96		0x04
#define	FFOSZ_I_128		0x05
#define	FFOSZ_I_160		0x06
#define	FFOSZ_I_192		0x07
#define	FFOSZ_I_256		0x08
#define	FFOSZ_I_320		0x09
#define	FFOSZ_I_384		0x0A
#define	FFOSZ_I_512		0x0B
#define	FFOSZ_I_640		0x0C
#define	FFOSZ_I_768		0x0D
#define	FFOSZ_I_896		0x0E
#define	FFOSZ_I_1023	0x0F

#define	FIFODISABLE	0x00

//						Address 
#define	DEVEN			0x80

//						Mode
#define	DMAWD_16		0x80
#define	GOSUSP		0x20
#define	INTENA			0x08
#define	DBGMOD		0x04
#define	SOFTCT			0x01

//						Hardware Configuration
#define	EXTPUL			0x4000
#define	NOLAZY			0x2000
#define	CLKRUN			0x1000
#define	CKDIV_48		0x0000
#define	DAKOLY			0x0080
#define	DRQPOL			0x0040
#define	DAKPOL			0x0020
#define	EOTPOL			0x0010
#define	WKUPCS		0x0008
#define	PWROFF		0x0004
#define	INTEDGE			0x0002
#define	INTPOL			0x0001

//						Interrupt
#define	EP14			0x00800000UL
#define	EP13			0x00400000UL
#define	EP12			0x00200000UL
#define	EP11			0x00100000UL
#define	EP10			0x00080000UL
#define	EP9				0x00040000UL
#define	EP8				0x00020000UL
#define	EP7				0x00010000UL
#define	EP6				0x00008000UL
#define	EP5				0x00004000UL
#define	EP4				0x00002000UL
#define	EP3				0x00001000UL
#define	EP2				0x00000800UL
#define	EP1				0x00000400UL
#define	EP0IN			0x00000200UL
#define	EP0OUT			0x00000100UL
#define	BUSTATUS		0x00000080UL
#define	PSOF			0x00000020UL
#define	SOF				0x00000010UL
#define	EOT				0x00000008UL
#define	SUSP			0x00000004UL
#define	RESM			0x00000002UL
#define	RST				0x00000001UL

//						DMA
#define	CNTREN			0x8000
#define	SHORTP			0X4000
//#define	EPDIX
#define	DMAEN			0x0008
#define	BURST_1		0x0000
#define	BURST_4		0x0001
#define	BURST_8		0x0002
#define	BURST_16		0x0003

//						Initialization Command value
//						Endpoint Configuration
#define	Ep0_Out_Value	(FIFOEN | FFOSZ_64)
#define	Ep0_In_Value		(FIFOEN | DIR_IN | FFOSZ_64)
//						Mode
#define	Mode_Value		(DMAWD_16 | INTENA | SOFTCT)
//						Hardware Configuration


//#define	Hw_Cfg_Value	(EXTPUL | NOLAZY | CLKRUN | CKDIV_48 | DRQPOL | WKUPCS | EOTPOL | PWROFF | INTPOL )
#define	Hw_Cfg_Value	(EXTPUL | NOLAZY |          CKDIV_48 | DRQPOL | WKUPCS | EOTPOL | PWROFF | INTPOL )


//						Interrupt Enable
//#define	Int_Enable_Value	(EP0IN | EP0OUT |  SUSP | RESM | RST)
#define	Int_Enable_Value	(EP0IN | EP0OUT | EP3 | EP4 |  SUSP | RESM | RST )
//#define	Int_Enable_Value	(EP0IN | EP0OUT | PSOF | SOF | SUSP | RESM | RST)
//#define	Int_Enable_Value	(EP0IN | EP0OUT | SOF | SUSP | RESM | RST)
//#define	Int_Enable_Value	(EP0IN | EP0OUT | SOF )
//#define	Int_Enable_Value	(EP0IN | EP0OUT )
//#define	Int_Enable_Value	(EP0IN | EP0OUT | PSOF | SUSP | RESM | RST)
//						DMA Configuration
#define	DMA_Cfg_Value	0x0000

void Comm( unsigned short command_code);
void Comm_w16(unsigned short command_code, unsigned short value);
void Comm_w32(unsigned short command_code, unsigned long value);
void Comm_w(unsigned short command_code, unsigned short length, unsigned short *buf);
unsigned short Comm_r16(unsigned short command_code);
unsigned long Comm_r32(unsigned short command_code);
unsigned short Comm_r(unsigned short command_code, unsigned short *buf);
unsigned short change_endian(unsigned short value);



#endif