tb_uart.vhd

uart_061109.rar

-----------------------------------------------
-- Design unit : testbench for uart.vhd 
--
-- File name   : tb_uart.vhd
--
-- Description :test transmitter operator
--
-- Limitations :
--
-- Author      : sweetpig
--
-- Revision    : Version 1.0  2006/11/8 
-----------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.amba.all;
--pragma translate_off
use ieee.std_logic_unsigned.conv_integer;
use STD.TEXTIO.all;
--pragma translate_on

entity tb_uart is
--generic (
	--PDMAX	  	: integer:=32;		-- Data max width
	--PAMAX	   : integer:=32		-- address max bits 
   --);
end;

architecture testbench of tb_uart is

  component uart is
   --generic (
	--PDMAX	  	: integer:=32;		-- Data max width
	--PAMAX	   : integer:=32		-- address max bits 
   --);
  port (
      rst    : in  std_logic;
      clk    : in  clk_type;
      apbi   : in  apb_slv_in_type;
      apbo   : out apb_slv_out_type;
      uarti  : in  uart_in_type;
      uarto  : out uart_out_type
    );
  end component uart; 
  
  --clk and rst signal
  Signal rst    : std_logic;
  Signal clk    : std_logic := '0';--initialize clock,otherwise it wii be uncertain--clk_type
  
  --Signal apbi   : apb_slv_in_type; 
  Signal PSEL    : std_ulogic;
  Signal PENABLE    : std_ulogic;
  Signal PADDR    : Std_Logic_Vector(PAMAX-1 downto 0);
  Signal PWRITE    : std_ulogic;
  Signal PWDATA    : Std_Logic_Vector(PDMAX-1 downto 0);
  
  --Signal apbo   : apb_slv_out_type;
  Signal PRDATA:    Std_Logic_Vector(PDMAX-1 downto 0);
  
  --Signal uarti  : uart_in_type; 
  Signal rxd   	: std_logic;
  Signal ctsn   : std_logic;--clear to send,active low
  Signal scaler	: std_logic_vector(7 downto 0);
  
  --Signal uarto  : uart_out_type
  Signal rxen    	: std_logic;
  Signal txen    	: std_logic;
  Signal flow   	: std_logic;
  Signal irq   	: std_logic;
  Signal rtsn   	: std_logic;
  Signal txd   	: std_logic;
  

 begin
 --DUT : uart Port map (rst,clk,apbi, apbo,uarti,uarto); 
 DUT : uart Port map(
    rst=>rst,
    clk=>clk,
    apbi.PSEL=>PSEL,
    --PSEL<=apbi_now.PSEL,
    apbi.PENABLE=>PENABLE,
    apbi.PADDR=>PADDR,
    apbi.PWRITE=>PWRITE,
    apbi.PWDATA=>PWDATA,
    apbo.PRDATA=>PRDATA,
    uarti.rxd=>rxd,
    uarti.ctsn=>ctsn,
    uarti.scaler=>scaler,
    uarto.rxen=>rxen,
    uarto.txen=>txen,
    uarto.flow=>flow,
    uarto.irq=>irq,
    uarto.rtsn=>rtsn,
    uarto.txd=>txd
    ); 
 
    clk<=not clk after 5 ns;
    rst<='0','1' after 100 ns,'0' after 150 ns;
    
   	    process
   	    --fileline variable
   	    variable inline:line;
   	    variable outline:line;

   	    --input variable
   	    variable PSEL_var :bit;
   	    variable PENABLE_var :bit;
   	    variable PADDR_var :bit_vector(PAMAX-1 downto 0);
   	    variable PWRITE_var :bit;
   	    variable PWDATA_var :bit_vector(PDMAX-1 downto 0);
   	    
   	    variable rxd_var :bit;
   	    variable ctsn_var :bit;
   	    variable scaler_var :bit_vector(7 downto 0); 	    
   	    
   	    --output variable
   	    variable PRDATA_var :bit_vector(PDMAX-1 downto 0);

   	    variable rxen_var :bit;
   	    variable txen_var :bit;
   	    variable flow_var :bit;
   	    variable irq_var :bit;
   	    variable rtsn_var :bit;
   	    variable txd_var :bit;
   	       	     
   	    --File where the input stimuli  are stored
        file infiles: text open read_mode is "input.txt";
        --File where the output results are written
        file outfiles: text open write_mode is "output.txt";
                  
   	    begin 
   	        --write the title
   	        write (outline,string'("PRDATA  rxen  txen  flow  irq  rtsn  txd"));
   	        writeline(outfiles,outline);
   	        
   	        --Read input stimuli and write output result
   	        while not endfile(infiles) loop
   	            
   	            --Read input stimuli
   	            readline(infiles,inline);
   	            if inline(1)='#' then
   	                next;
   	            end if;
   	            read(inline, PSEL_var);
   	            PSEL<=to_stdulogic(PSEL_var);
   	            read(inline, PENABLE_var);
   	            PENABLE<=to_stdulogic(PENABLE_var);
   	            read(inline, PADDR_var);
   	            PADDR<=to_stdlogicvector(PADDR_var);
   	            read(inline, PWRITE_var);
   	            PWRITE<=to_stdulogic(PWRITE_var);
   	            read(inline, PWDATA_var);
   	            PWDATA<=to_stdlogicvector(PWDATA_var); 
   	            read(inline, rxd_var);
   	            rxd<=to_stdulogic(rxd_var); 
   	            read(inline, ctsn_var);
   	            ctsn<=to_stdulogic(ctsn_var); 
   	            read(inline, scaler_var);
   	            scaler<=to_stdlogicvector(scaler_var); 
   	              	            
   	            --write output result
   	            write(outline,to_bitvector(PRDATA));
   	            write(outline,string'(" "));
   	            write(outline,to_bit(rxen));
   	            write(outline,string'(" "));
   	            write(outline,to_bit(txen));
   	            write(outline,string'(" "));
   	            write(outline,to_bit(flow));
   	            write(outline,string'(" "));
   	            write(outline,to_bit(irq));
   	            write(outline,string'(" "));
   	            write(outline,to_bit(rtsn));
   	            write(outline,string'(" "));
   	            write(outline,to_bit(txd));
   	            write(outline,string'(" "));
   	            
   	            writeline(outfiles,outline);
   	            
   	            wait until clk='1';
   	        end loop;
   	        wait;
   	    end process;
   	    end architecture testbench;