year_c.v

来自「用vierilog语言描写的电子时钟源码」· Verilog 代码 · 共 35 行

//BCD计数器，从0计到0x99(BCD)
module	year_c(reset,clk,q,cout);
input			reset,clk;
output cout;
output	[7:0]	q;

reg cout;
reg		[7:0]	q;
always	@(posedge clk or negedge reset)
   begin
     if(!reset)
       begin 		
         q<=8'd1;
         cout<=0;
       end
     else if(q==8'd18)
       begin		
         q<=8'd1;
         cout<=1;
       end
     else
	begin
	  cout<=0;
         if(q[3:0]==4'd9)
	     begin					//bcd format
		q[3:0]<=4'd0;
		q[7:4]<=q[7:4]+1;
	     end
	  else
		q<=q+1;
	end
   end
endmodule