scan.v

用vierilog语言描写的电子时钟源码

module scan(clk,input1,input2,input3,input4,input5,input6,scan,out);
input clk;
input [4:0] input1,input2,input3,input4,input5,input6;
output [7:0] out;
output [5:0] scan;

wire [5:0] scan,scan1;
wire [7:0] out;

reg [4:0] seg_out;
reg [2:0] count_scan;

wire [7:0] scan_cs_temp;

always @(posedge clk)
      begin
           case(count_scan)
                 0:  begin
                          count_scan<=1;
                          seg_out<=input2;
                     end
                 1:  begin
                          count_scan<=2;
                          seg_out<=input3;
                     end
                 2:  begin
                          count_scan<=3;
                          seg_out<=input4;
                     end
                 3:  begin
                          count_scan<=4;
                          seg_out<=input5;
                     end
                 4:  begin
                          count_scan<=5;
                          seg_out<=input6;
                     end
                 5:  begin
                          count_scan<=0;
                          seg_out<=input1;
                     end  
           default:  begin
                          count_scan<=0;
                          seg_out<=input1;
                     end 
           endcase
      end
assign scan[0]=~scan1[0];
assign scan[1]=~scan1[1];
assign scan[2]=~scan1[2];
assign scan[3]=~scan1[3];
assign scan[4]=~scan1[4];
assign scan[5]=~scan1[5];

assign scan1=scan_cs_temp[5:0];
three_eight u1(count_scan,scan_cs_temp);
seven_seg u2(seg_out,out);

endmodule