timer.v

用vierilog语言描写的电子时钟源码

module timer(glbclk,clk,stop,reset,dm,m,ds,s,dms,ms);
input glbclk,clk,stop,reset;
output [3:0] dm,m,ds,s,dms,ms;

wire reset,c_msec,c_dmsec,c_sec,c_dsec,c_min,c_dmin,c_hour;
reg msec;


always @(glbclk)
begin
  if (stop)
         msec=0;
  else
         msec=clk;
end
up_count_10 clk100(msec,reset,co,c_msec);
up_count_10 clkms(c_msec,reset,ms,c_dmsec);
up_count_10 clkdms(c_dmsec,reset,dms,c_sec);    
up_count_10 clks(c_sec,reset,s,c_dsec);
up_count_6 countsecd(c_dsec,reset,ds,c_min);
up_count_10 countmin(c_min,reset,m,c_dmin);
up_count_6 countmind(c_dmin,reset,dm,c_hour);
endmodule