seven_seg.v
来自「用vierilog语言描写的电子时钟源码」· Verilog 代码 · 共 30 行
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30 行
module seven_seg(binary_code,segment_out);
input [4:0] binary_code;
output [7:0] segment_out;
reg[7:0] segment_out;
always @(binary_code)
begin
case(binary_code[3:0])
4'd0: segment_out[6:0]=7'b1111110;
4'd1: segment_out[6:0]=7'b0110000;
4'd2: segment_out[6:0]=7'b1101101;
4'd3: segment_out[6:0]=7'b1111001;
4'd4: segment_out[6:0]=7'b0110011;
4'd5: segment_out[6:0]=7'b1011011;
4'd6: segment_out[6:0]=7'b1011111;
4'd7: segment_out[6:0]=7'b1110000;
4'd8: segment_out[6:0]=7'b1111111;
4'd9: segment_out[6:0]=7'b1111011;
4'd10: segment_out[6:0]=7'b1110111;
4'd11: segment_out[6:0]=7'b0011111;
4'd12: segment_out[6:0]=7'b1001110;
4'd13: segment_out[6:0]=7'b0111101;
4'd14: segment_out[6:0]=7'b1001111;
4'd15: segment_out[6:0]=7'b1000111;
default: segment_out[6:0]=7'b0000001;
endcase
segment_out[7]=binary_code[4];
end
endmodule
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