au.v

来自「用vierilog语言描写的电子时钟源码」· Verilog 代码 · 共 35 行

module au(clk,reset);
input clk;
reg [15:0] counter;
output reset;
reg reset;
`define abc
`ifdef abc
       initial
         begin
            reset=1;
            counter=16'h5500;
         end
`endif
      always @(posedge clk)
      begin
          if(counter>=16'h5555&&counter<=16'haaaa)
                 begin
                      counter<=counter+1;
                      reset<=0;
                 end
           else 
                 if(counter==16'haaab)
                 begin
                 reset<=1;
                 end
           else  if(counter>16'haaab)
                 begin
                 counter<=0;
                 reset<=1;
                 end
           else
                 counter<=counter+1;
      end
endmodule