up_count_7.v

来自「用vierilog语言描写的电子时钟源码」· Verilog 代码 · 共 29 行

module up_count_7(clk,reset,q,cout);

input clk,reset;
output [3:0] q;
output cout;

reg [3:0] q;
reg cout;

always @(posedge clk or negedge reset)
      begin
            if (!reset)
                 begin 
                     q<=1;
                     cout<=0;
                 end
            else 
                 if (q==7)
                       begin
                            q<=1;
                            cout<=1;
                       end
                 else
                       begin
                            q<=q+1;
                            cout<=0;
                       end
       end
endmodule