sd_reg.h.bak

怎么样操作flash

//;; register address in DMA1
#define DMA1DATA_LEN0		0x4000
#define DMA1DATA_LEN1		0x4001
#define DMA1D_LEN_WID		10
#define DMA1START_A0		0x4002
#define DMA1START_A1		0x4003
#define DMA1CTRL			0x4004
#define DMA_START_BIT		0
#define DMA_SEND_BIT		1
#define DMA_STOP_BIT		2
#define DMA1STATUS		  	0x4008
#define DMA_DONE_BIT	 	0

#define DMA_REG_SEL		0x40

//;; register address in DMA2
#define DMA2DATA_LEN0		0x4010
#define DMA2DATA_LEN1		0x4011
#define DMA2D_LEN_WID		10
#define DMA2START_A0		0x4012
#define DMA2START_A1		0x4013
#define DMA2CTRL			0x4014
#define DMA2STATUS		  	0x4018

//;; register address in SD interface
#define CSD_ADDR1		0x4101
#define CSD_ADDR2		0x4102
#define CSD_ADDR3		0x4103
#define CSD_ADDR4		0x4104
#define CSD_ADDR5		0x4105
#define CSD_ADDR6		0x4106
#define CSD_ADDR7		0x4107
#define CSD_ADDR8		0x4108
#define CSD_ADDR9		0x4109
#define CSD_ADDR10		0x410A
#define CSD_ADDR11		0x410B
#define CSD_ADDR12		0x410C
#define CSD_ADDR13		0x410D
#define CSD_ADDR14		0x410E
#define CSD_ADDR15		0x410F
#define CID_ADDR1		0x4141
#define CID_ADDR2		0x4142
#define CID_ADDR3		0x4143
#define CID_ADDR4		0x4144
#define CID_ADDR5		0x4145
#define CID_ADDR6		0x4146
#define CID_ADDR7		0x4147
#define CID_ADDR8		0x4148
#define CID_ADDR9		0x4149
#define CID_ADDR10		0x414A
#define CID_ADDR11		0x414B
#define CID_ADDR12		0x414C
#define CID_ADDR13		0x414D
#define CID_ADDR14		0x414E
#define CID_ADDR15		0x414F

#define OCR_ADDR0		0x4110
#define OCR_ADDR1		0x4111
#define OCR_ADDR2		0x4112
#define OCR_ADDR3		0x4113
#define RCA_ADDR0		0x4114
#define RCA_ADDR1		0x4115
#define DSR_ADDR0		0x4116
#define DSR_ADDR1		0x4117
#define CSR_ADDR0		0x4118
#define CSR_ADDR1		0x4119
#define CSR_ADDR2		0x411A
#define CSR_ADDR3		0x411B

#define OUT_OF_RANGE_BIT	7
#define ADDR_ERR_BIT		6
#define BLK_LEN_ERR_BIT		5
#define ERASE_SEQ_ERR_BIT	4
#define ERASE_PARAM_BIT		3
#define WP_VIOLATE_BIT		2
#define CARD_LOCKED_BIT		1
#define LOCK_UNL_FAIL_BIT	0
#define COM_CRC_ERR_BIT		7
#define ILLEGAL_CMD_BIT		6
#define CARD_ECC_FAIL_BIT	5
#define CC_ERR_BIT			4
#define ERROR_BIT			3
#define CSD_OVERWR_BIT		0
#define WP_ERASE_SKIP_BIT	7
#define CARD_ECC_DIS_BIT	6
#define ERASE_RESET_BIT		5
#define CURRENT_ST_BITS		0x1e
#define RDY_FOR_DATA_BIT	0
#define CSR_APP_CMD_BIT		5
#define AKE_SEQ_ERR_BIT		3

#define SD_CONTROL				0x411C
#define SPI_MODE_BIT		    0
#define SPI_PROT_BIT		    1
#define D_BUS_WID_BIT	   		2
#define FL_PRG_ERR_BIT		    3
#define WR_PROTED		      	4
#define CONN50K_BIT		    	5
#define HIGH_SPEED_BIT	  		6
#define SET_BUSY_BIT		   	7
#define SD_CONTROL1				0x411D
#define CLR_CMD_V_BIT	   		0
#define CLR_DATA_V_BIT	  		1
#define DATA_START_BIT   		2
#define CLR_PULLUP_BIT   		3
#define DATA_ERR_TOKEN		 	4
#define CLR_RSP_BUSY			5
#define SD_CONTROL2				0x411E
#define MULTI_BLK_BIT		  	0

#define SD_STATUS0				0x4120
#define CMD_RCVING_BIT			0
#define CMD_RCVED_BIT			1
#define CMD_VALID_BIT			2
#define GOTO_SPI_BIT			3
#define RESPONSING_BIT			4
#define RESP_DONE_BIT			5
#define DATA_SENDING_BIT		6
#define DATA_SENT_BIT			7
#define SD_STATUS1				0x4121
#define DATA_RCVING_BIT			0
#define DATA_RCVED_BIT			1
#define DATA_VALID_BIT			2
#define CRC_BUSY_BIT			3
//;;#define CMD_INT_BIT			4
//;;#define DATA_DONE_BIT			5
#define APP_CMD_BIT				4
#define CMD8RCVED_BIT			6
#define INA_ST_BIT				7

#define CMD_REG1			0x4129
#define CMD_REG2			0x412A
#define CMD_REG3			0x412B
#define CMD_REG4			0x412C
#define CMD_REG5			0x412D
#define BLK_LEN0			0x412E
#define BLK_LEN1			0x412F
#define BLK_LEN_WID			12

#define NO_WR_BLK0			0x4130
#define NO_WR_BLK1			0x4131
#define NO_WR_BLK2			0x4132
#define NO_WR_BLK3			0x4133

#define SD_REG_SEL			0x41

//;; register address in FLASH interface
#define FL_CTRL0			0x4200
#define FL_CSN_BITS   0xf
#define FL_WRN_BIT    4
#define FL_RDN_BIT    5
#define FL_CLE_BIT    6
#define FL_ALE_BIT    7
#define FL_CTRL1			0x4201
#define FL_WR_CYCLES  0x7
#define FL_WR_CYC2	  0x0
#define MAX_FL_CYCLES 7
#define FL_WPN_BIT    3
#define CAL_LOG_A_BIT	4
#define RW_ECC_BIT    5
#define BYTE_NUMS     0xe0
#define BYTE_NUMS2    0x00
#define FL_STATUS			0x4204
#define FL_RB_BITS    0x3
#define RW_DONE_BITS  2

#define LOG_A0		0x4208
#define LOG_A1		0x4209
#define LOG_A2		0x420a
#define LOG_A3		0x420b
#define LOG_A4		0x420c
#define LOG_A5		0x420d

#define FL_DATA		0x7f00

//;; register address in ECC interface
#define ECC_REG_A		   	0x4280
#define ECC_CTRL			0x4281
#define ECC_GEN_BIT			0
#define ECC_DEC_BIT			1
#define ECC_CHECK_BIT		2
#define ECC_CALEN_BIT		3
#define ECC_CLR_BIT			4

#define ECC_DATA0		   	0x4282
#define ECC_DATA1		   	0x4283

#define ECC_REG_SEL			0x42