mcu_def.h

怎么样操作flash

//#define piop 0x98

//; bit selection for BSET operation
#define bit_set7 	0x87
#define bit_set6	0x86
#define bit_set5	0x85
#define bit_set4	0x84
#define bit_set3	0x83
#define bit_set2	0x82
#define bit_set1	0x81
#define bit_set0	0x80

//; bit selection for BCLR operation
#define bit_clr7	0x47
#define bit_clr6	0x46
#define bit_clr5	0x45
#define bit_clr4	0x44
#define bit_clr3	0x43
#define bit_clr2	0x42
#define bit_clr1	0x41
#define bit_clr0	0x40

#define IN_IDLE_ST_clr	0x47

//; bit selection for BTEST operation
#define bit_test7	0x27
#define bit_test6	0x26
#define bit_test5	0x25
#define bit_test4	0x24
#define bit_test3	0x23
#define bit_test2	0x22
#define bit_test1	0x21
#define bit_test0	0x20

//; SD_CONTROL's bset
#define SPI_MODE_set		    0x80
#define SPI_PROT_set		    0x81
#define four_bit_bus_set	   		0x82
#define FL_PRG_ERR_set		    0x83
#define WR_PROTED_set		    0x84
#define CONN50K_set		    	0x85
#define HIGH_SPEED_set	  		0x86
#define SET_BUSY_set		   	0x87
//; SD_CONTROL1's bset
#define CLR_CMD_V_set	   		0x80
#define CLR_DATA_V_set	  		0x81
#define DATA_START_set   		0x82
#define CLR_PULLUP_set   		0x83
#define DATA_ERR_TOKEN_set		0x84
#define CLR_RSP_BUSY_set		0x85
//; SD_CONTROL2's bset
#define MULTI_BLK_set		  	0x80

//; DMA's bset and bclr
#define DMA_SEND_set			0x81
#define DMA_SEND_clr			0x41
#define DMA_START_set			0x80

//; SD_CONTROL's bclr
#define SPI_MODE_clr		    0x40
#define SPI_PROT_clr		    0x41
#define four_bit_bus_clr	   		0x42
#define FL_PRG_ERR_clr		    0x43
#define WR_PROTED_clr		    0x44
#define CONN50K_clr		    	0x45
#define HIGH_SPEED_clr	  		0x46
#define SET_BUSY_clr		   	0x47
//; SD_CONTROL2's bclr
#define MULTI_BLK_clr		  	0x40

//; SD_STATUS0's bit test
#define CMD_RCVING_test			0x20
#define CMD_RCVED_test			0x21
#define CMD_VALID_test			0x22
#define GOTO_SPI_test			0x23
#define RESPONSING_test			0x24
#define RSP_DONE_test			0x25
#define DATA_SENDING_test		0x26
#define DATA_SENT_test			0x27
//; SD_STATUS1's bit test
#define DATA_RCVING_test		0x20
#define DATA_RCVED_test			0x21
#define DATA_VALID_test			0x22
#define CRC_BUSY_test			0x23
#define APP_CMD_test			0x24
#define RSP_BUSY_test			0x25
#define CMD8RCVED_test			0x26
#define INA_ST_test				0x27

//;; set current status
#define set_CS_IDLE		   	0x10
#define set_CS_READY		0x11
#define set_CS_IDENT		0x12
#define set_CS_STBY		   	0x13
#define set_CS_TRAN		   	0x14
#define set_CS_DATA		   	0x15
#define set_CS_RCV		    0x16
#define set_CS_PRG		    0x17
#define set_CS_DIS		    0x18
#define set_CS_INA		    0x1e

//; RAM varible bits
#define prging_st			8
#define need_data			prging_st+1
#define multi_blocks		need_data+1

#define block_len			0x32
#define erase_count			block_len+2
#define pre_cmd				erase_count+1
#define inc_offset			pre_cmd+1


 //;; register address in FLASH interface
//; FL_CTRL0			
#define FL_CSN0_set   0x80
#define FL_CSN1_set   0x81
#define FL_CSN2_set   0x82
#define FL_CSN3_set   0x83
#define FL_WRN_set    0x84
#define FL_RDN_set    0x85
#define FL_CLE_set    0x86
#define FL_ALE_set    0x87
#define FL_CSN0_clr   0x40
#define FL_CSN1_clr   0x41
#define FL_CSN2_clr   0x42
#define FL_CSN3_clr   0x43
#define FL_WRN_clr    0x44
#define FL_RDN_clr    0x45
#define FL_CLE_clr    0x46
#define FL_ALE_clr    0x47
//; FL_CTRL1	
#define FL_WPN_set    0x83
#define CAL_LOG_set   0x84
#define RW_ECC_set    0x85
#define FL_WPN_clr    0x43
#define CAL_LOG_clr   0x44
#define RW_ECC_clr    0x45
//; FL_STATUS			
#define FL_RB0_test   0x20
#define FL_RB1_test   0x21
#define RW_DONE_test  0x22

//; DMA_STATUS
#define DMA_DONE_test 0x20

//;; register address in ECC interface
//; ECC_CTRL			0x4281
#define ECC_GEN_set			0x80
#define ECC_DEC_set			0x81
#define ECC_CHECK_set		0x82
#define ECC_CALEN_set		0x83
#define ECC_CLR_set			0x84
#define ECC_GEN_clr			0x40
#define ECC_DEC_clr			0x41

#define ecc_busy	0x23
#define ecc_err		0x24