📄 main.lst
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C51 COMPILER V7.50 MAIN 09/29/2007 17:25:28 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE main.C BROWSE DEBUG OBJECTEXTEND
line level source
1
2 #include <reg51.h>
3 #include "mcu_def.h"
4 #include "sd_reg.h"
5 #define FL_ALE_SET() DPL = FL_CTRL0; DPH = 0x42; PIOP = 0x87;
6 #define FL_ALE_CLR() DPL = FL_CTRL0; DPH = 0x42; PIOP = 0x47;
7 sfr PIOP = 0x98;
8 sbit psw1 = PSW^1;
9 void wait_rb(void);
10 void fl_cmd(unsigned char cmd);
11
12
13 volatile unsigned char xdata fl_data _at_ 0x7f00;
14 volatile unsigned char xdata ff_data _at_ 0x8f00;
15
16 //flash reg
17 volatile unsigned char xdata fl_CTRL0 _at_ 0x4200;
18 volatile unsigned char xdata fl_CTRL1 _at_ 0x4201;
19 //dma2
20 volatile unsigned char xdata dma2_LEN0 _at_ 0x4010;
21 volatile unsigned char xdata dma2_LEN1 _at_ 0x4011;
22 volatile unsigned char xdata dma2_A0 _at_ 0x4012;
23 volatile unsigned char xdata dma2_A1 _at_ 0x4013;
24
25 volatile unsigned char xdata flash_LOG_A0 _at_ 0x4208;
26 volatile unsigned char xdata flash_LOG_A1 _at_ 0x4209;
27 volatile unsigned char xdata flash_LOG_A2 _at_ 0x420a;
28 volatile unsigned char xdata flash_LOG_A3 _at_ 0x420b;
29 volatile unsigned char xdata flash_LOG_A4 _at_ 0x420c;
30 volatile unsigned char xdata flash_LOG_A5 _at_ 0x420d;
31
32 volatile unsigned char xdata *p;
33 int i;
34 main()
35 {
36 1 unsigned char n1,n2,n3,n4,n5,status,ram_data;
37 1
38 1 for (i=0,p = 0; i<512; i++,p++)
39 1 *p = i + 1;
40 1
41 1 for (i=0,p = 0; i<512; i++,p++)
42 1 {
43 2 ram_data = *p;
44 2 i = i;
45 2 }
46 1
47 1 fl_CTRL1 = 0x0c;
48 1 fl_CTRL0 = 0x3e;
49 1 wait_rb();
50 1
51 1 //read ID
52 1
53 1 fl_cmd(0x90);
54 1 FL_ALE_SET();
55 1 fl_data = 0X00;
C51 COMPILER V7.50 MAIN 09/29/2007 17:25:28 PAGE 2
56 1 FL_ALE_CLR();
57 1
58 1 ff_data = 0x00;
59 1
60 1 n1 = fl_data;
61 1 ff_data = 0x00;
62 1 n2 = fl_data;
63 1 ff_data = 0x00;
64 1 n3 = fl_data;
65 1 ff_data = 0x00;
66 1 n4 = fl_data;
67 1 ff_data = 0x00;
68 1 n5 = fl_data;
69 1
70 1 //ERASE FLASH
71 1 fl_cmd(0x60);
72 1
73 1 FL_ALE_SET();
74 1 fl_data = 0X00; //ROW ADDR1
75 1 ff_data = 0x00;
76 1 fl_data = 0X00; //ROW ADDR2
77 1 ff_data = 0x00;
78 1 fl_data = 0X00; //ROW ADDR3
79 1 ff_data = 0x00;
80 1 FL_ALE_CLR();
81 1
82 1 fl_cmd(0xD0);
83 1
84 1 wait_rb();
85 1
86 1 //read status
87 1 fl_cmd(0x70);
88 1 status = fl_data;
89 1
90 1 flash_LOG_A0 = 0x11;
91 1 flash_LOG_A1 = 0x22;
92 1 flash_LOG_A2 = 0x33;
93 1 flash_LOG_A3 = 0x44;
94 1 flash_LOG_A4 = 0x55;
95 1 flash_LOG_A5 = 0x66;
96 1
97 1 //write flash
98 1 fl_cmd(0x80);
99 1
100 1 FL_ALE_SET();
101 1 fl_data = 0X00; //column ADDR1
102 1 ff_data = 0x00;
103 1 fl_data = 0X00; //column ADDR2
104 1 ff_data = 0x00;
105 1 fl_data = 0X00; //ROW ADDR1
106 1 ff_data = 0x00;
107 1 fl_data = 0X00; //ROW ADDR2
108 1 ff_data = 0x00;
109 1 fl_data = 0X00; //ROW ADDR3
110 1 ff_data = 0x00;
111 1 FL_ALE_CLR();
112 1
113 1 DPL = FL_CTRL1;
114 1 DPH = 0x42;
115 1 PIOP = RW_ECC_set;
116 1
117 1 DPL = FL_CTRL1;
C51 COMPILER V7.50 MAIN 09/29/2007 17:25:28 PAGE 3
118 1 DPH = 0x42;
119 1 PIOP = CAL_LOG_set;
120 1
121 1 dma2_LEN0 = 0x80;
122 1 dma2_LEN1 = 0;
123 1 dma2_A0 = 0;
124 1 dma2_A1 = 0;
125 1
126 1 DPL = DMA2CTRL;
127 1 DPH = 0x40;
128 1 PIOP = DMA_SEND_set;
129 1
130 1 DPL = DMA2CTRL;
131 1 DPH = 0x40;
132 1 PIOP = DMA_START_set;
133 1
134 1 //ecc control
135 1 DPL = ECC_CTRL;
136 1 DPH = 0x42;
137 1 PIOP = ECC_CLR_set;
138 1
139 1 DPL = ECC_CTRL;
140 1 DPH = 0x42;
141 1 PIOP = ECC_GEN_set;
142 1
143 1
144 1 //start flash write
145 1 DPL = FL_CTRL0;
146 1 DPH = 0x42;
147 1 PIOP = FL_WRN_clr;
148 1
149 1 //wait for DMA done
150 1 DPL = DMA2STATUS;
151 1 DPH = 0x40;
152 1 PIOP = DMA_DONE_test;
153 1 while (!psw1)
154 1 PIOP = DMA_DONE_test;
155 1 //wait for flash-write done
156 1 DPL = FL_STATUS;
157 1 DPH = 0x42;
158 1 PIOP = RW_DONE_test;
159 1 while (!psw1)
160 1 PIOP = RW_DONE_test;
161 1 //stop flash write
162 1 DPL = FL_CTRL0;
163 1 DPH = 0x42;
164 1 PIOP = FL_WRN_set;
165 1
166 1 DPL = ECC_CTRL;
167 1 DPH = 0x42;
168 1 PIOP = ECC_GEN_clr;
169 1
170 1 fl_cmd(0x10);
171 1
172 1 wait_rb();
173 1
174 1 fl_cmd(0x70);
175 1 status = fl_data;
176 1
177 1 for (i=0; i<512; i++);
178 1
179 1 //read flash
C51 COMPILER V7.50 MAIN 09/29/2007 17:25:28 PAGE 4
180 1 fl_cmd(0x00);
181 1
182 1 FL_ALE_SET();
183 1 fl_data = 0X00; //column ADDR1
184 1 ff_data = 0x00;
185 1 fl_data = 0X00; //column ADDR2
186 1 ff_data = 0x00;
187 1 fl_data = 0X00; //ROW ADDR1
188 1 ff_data = 0x00;
189 1 fl_data = 0X00; //ROW ADDR2
190 1 ff_data = 0x00;
191 1 fl_data = 0X00; //ROW ADDR3
192 1 ff_data = 0x00;
193 1 FL_ALE_CLR();
194 1
195 1 fl_cmd(0x30);
196 1 wait_rb();
197 1
198 1 dma2_LEN0 = 0x80;
199 1 dma2_LEN1 = 0;
200 1 dma2_A0 = 0x90;
201 1 dma2_A1 = 0;
202 1
203 1 DPL = DMA2CTRL;
204 1 DPH = 0x40;
205 1 PIOP = DMA_SEND_clr;
206 1
207 1 DPL = DMA2CTRL;
208 1 DPH = 0x40;
209 1 PIOP = DMA_START_set;
210 1
211 1 //ecc control
212 1 DPL = ECC_CTRL;
213 1 DPH = 0x42;
214 1 PIOP = ECC_CLR_set;
215 1
216 1 DPL = ECC_CTRL;
217 1 DPH = 0x42;
218 1 PIOP = ECC_DEC_set;
219 1
220 1 //start flash write
221 1 DPL = FL_CTRL0;
222 1 DPH = 0x42;
223 1 PIOP = FL_RDN_clr;
224 1
225 1 //wait for DMA done
226 1 DPL = DMA2STATUS;
227 1 DPH = 0x40;
228 1 PIOP = DMA_DONE_test;
229 1 while (!psw1)
230 1 PIOP = DMA_DONE_test;
231 1 //wait for flash-write done
232 1 DPL = FL_STATUS;
233 1 DPH = 0x42;
234 1 PIOP = RW_DONE_test;
235 1 while (!psw1)
236 1 PIOP = RW_DONE_test;
237 1 //stop flash write
238 1 DPL = FL_CTRL0;
239 1 DPH = 0x42;
240 1 PIOP = FL_RDN_set;
241 1
C51 COMPILER V7.50 MAIN 09/29/2007 17:25:28 PAGE 5
242 1 DPL = ECC_CTRL;
243 1 DPH = 0x42;
244 1 PIOP = ECC_DEC_clr;
245 1
246 1 for (i=0,p = 0x0090; i<512; i++,p++)
247 1 {
248 2 ram_data = *p;
249 2 i = i;
250 2 }
251 1
252 1 while(1);
253 1
254 1
255 1
256 1
257 1
258 1
259 1
260 1
261 1
262 1
263 1
264 1
265 1
266 1 }
267
268 void wait_rb(void)
269 {
270 1 DPL = FL_STATUS;
271 1 DPH = 0x42;
272 1 PIOP = FL_RB0_test;
273 1 while (!psw1)
274 1 PIOP = FL_RB0_test;
275 1
276 1 }
277
278 void fl_cmd(unsigned char cmd)
279 {
280 1 DPL = FL_CTRL0;
281 1 DPH = 0x42;
282 1 PIOP = FL_CLE_set;
283 1 fl_data = cmd;
284 1 DPL = FL_CTRL0;
285 1 DPH = 0x42;
286 1 PIOP = FL_CLE_clr;
287 1
288 1 }
289 /*
290 void fl_ale_set(void)
291 {
292 DPL = FL_CTRL0;
293 DPH = 0x42;
294 PIOP = FL_CLE_set;
295 }
296
297 void fl_ale_clr(void)
298 {
299 DPL = FL_CTRL0;
300 DPH = 0x42;
301 PIOP = FL_ALE_clr;
302 }*/
C51 COMPILER V7.50 MAIN 09/29/2007 17:25:28 PAGE 6
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 738 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 4 7
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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