📄 regset.h
字号:
0x00, /*;REG af, RESERVE*/
0x00, /*;REG b0, vertical scaling increment for luminance*/
0x04, /*;REG b1, vertical scaling increment for luminance*/
0x00, /*;REG b2, vertical scaling increment for chrominace*/
0x04, /*;REG b3, vertical scaling increment for chrominace*/
0x00, /*;REG b4, vertical scaling mode control*/
0x00, /*;REG b5, reserved*/
0x00, /*;REG b6, RESERVE*/
0x00, /*;REG b7, RESERVE*/
0x00, /*;REG b8, vertical phase offsets luminance and chrominance*/
0x00, /*;REG b9, vertical phase offsets luminance and chrominance*/
0x00, /*;REG ba, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bb, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bc, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bd, vertical phase offsets luminance and chrominance*/
0x00, /*;REG be, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bf, vertical phase offsets luminance and chrominance*/
};
unsigned code saa7114ext[0xc0]=
{
0x00, /*;REG 00, Chip version*/
0x08, /*;REG 01, horizontal increment delay*/
0xc4, /*;REG 02, INPUT CONTROL 1, Mode 4 b4 */
0x33, /*;REG 03, INPUT CONCROL 2, 23H*/
0x00, /*;REG 04, GAIN CONTROL 1, gain1=00h*/
0x00, /*;REG 05, GAIN CONTROL 2, gain2=00h*/
0xfb, /*;REG 06, HS START EB 15H*/
0x9f, /*;REG 07, HS STOP*/
0x01, /*;REG 08, SYNC CONTROL*/ ///40h???
0x40, /*;REG 09, LUMINANCE CONTROL, COMB FILTER, 40h*/ ///a0h???
0x7e, /*;REG 0A, LUMINANCE BRIGHTNESS, CCIR level,80H 79h*/
0x42, /*;REG 0B, LUMINANCE CONTRAST, CCIR level, 44H 40h*/
0x3c, /*;REG 0C, CHROMINANCE SATURATION, CCIR level, 40H 36h*/
0x00, /*;REG OD, CHROMA HUE CONTROL, 0 degree*/
0x01, /*;REG 0E, CHROMINANCE CONTROL, */ ///89h???
0x2a, /*;REG 0F, CHROMINANCE GAIN CONTROL 2a*/
0x0e, /*;REG 10, CHROMINANCE LUMINACE CONTROL*/
0x08, /*;REG 11, MODE/DELAY CONTROL 00H*/
0x39, /*;REG 12, RTS0/RTS1 CONTROL */
0xc0, /*;REG 13, RT/X-PORT CONTROL, 00h*/
0x00, /*;REG 14, ADC COMPATIBILITY CONTROL*/
0xfd, /*;REG 15, VGATE START*/
0xfe, /*;REG 16, VGATE STOP*/
0x00, /*;REG 17, MISC VGATE MSB*/
0x40, /*;REG 18, RAW DATA GAIN CONTROL*/
0x80, /*;REG 19, RAW DATA OFFSET CONTROL*/
0x00, /*;REG 1A, RESERVE*/
0x00, /*;REG 1B, RESERVE*/
0x00, /*;REG 1C, RESERVE*/
0x00, /*;REG 1D, RESERVE*/
0x00, /*;REG 1E, RESERVE*/
0x00, /*;REG 1F, RESERVE*/
0x00, /*;REG 20, RESERVE*/
0x00, /*;REG 21, RESERVE*/
0x00, /*;REG 22, RESERVE*/
0x00, /*;REG 23, RESERVE*/
0x00, /*;REG 24, RESERVE*/
0x00, /*;REG 25, RESERVE*/
0x00, /*;REG 26, RESERVE*/
0x00, /*;REG 27, RESERVE*/
0x00, /*;REG 28, RESERVE*/
0x00, /*;REG 29, RESERVE*/
0x00, /*;REG 2A, RESERVE*/
0x00, /*;REG 2B, RESERVE*/
0x00, /*;REG 2C, RESERVE*/
0x00, /*;REG 2D, RESERVE*/
0x00, /*;REG 2E, RESERVE*/
0x00, /*;REG 2F, RESERVE*/
0x00, /*;REG 30, AUDIO MASTER CLOCK*/
0xc0, /*;REG 31, AUDIO MASTER CLOCK*/
0x03, /*;REG 32, audio master clock*/ //12.288M/50?
0x00, /*;REG 33, reserve*/
0xcd, /*;REG 34, audio master clock increment*/
0xcc, /*;REG 35, audio master clock increment*/
0x3a, /*;REG 36, audio master clock increment*/
0x00, /*;REG 37, reserve*/
0x03, /*;REG 38, clock ratio AMXCLK to ASCLK*/
0x20, /*;REG 39, clock ratio AMXCLK to ALRCLK*/
0x00, /*;REG 3A, AUDIO CLOCK generator*/
0x00, /*;REG 3B, RESERVE*/
0x00, /*;REG 3C, RESERVE*/
0x00, /*;REG 3D, RESERVE*/
0x00, /*;REG 3E, RESERVE*/
0x00, /*;REG 3F, RESERVE*/
0x00, /*;REG 40, slicer control 1*/
0xff, /*;REG 41, LCR2*/
0xff, /*;REG 42, LCR3*/
0xff, /*;REG 43, LCR4*/
0xff, /*;REG 44, LCR5*/
0xff, /*;REG 45, LCR6*/
0xff, /*;REG 46, LCR7*/
0xff, /*;REG 47, LCR8*/
0xff, /*;REG 48, LCR9*/
0xff, /*;REG 49, LCR10*/
0xff, /*;REG 4A, LCR11*/
0xff, /*;REG 4B, LCR12*/
0xff, /*;REG 4C, LCR13*/
0xff, /*;REG 4D, LCR14*/
0xff, /*;REG 4E, LCR15*/
0xff, /*;REG 4F, LCR16*/
0xff, /*;REG 50, LCR17*/
0xff, /*;REG 51, LCR18*/
0xff, /*;REG 52, LCR19*/
0xff, /*;REG 53, LCR20*/
0xff, /*;REG 54, LCR21*/
0xff, /*;REG 55, LCR22*/
0xff, /*;REG 56, LCR23*/
0xff, /*;REG 57, LCR24*/
0x00, /*;REG 58, prog. frame code*/
0x47, /*;REG 59, horizontal offset for slicer*/
0x06, /*;REG 5A, vertical offset for slicer*/
0x03, /*;REG 5b, field offset MSB for horizontal and vertical*/
0x00, /*;REG 5c,reserve */
0x00, /*;REG 5d, RESERVE*/
0x00, /*;REG 5e, sliced data ident code*/
0x00, /*;REG 5f, reserved*/
0x00, /*;REG 60,slicer status byte1 */
0x00, /*;REG 61,slicer status byte2 */
0x00, /*;REG 62,slicer status byte3 */
0x00, /*;REG 63, RESERVE*/
0x00, /*;REG 64, RESERVE*/
0x00, /*;REG 65, RESERVE*/
0x00, /*;REG 66, RESERVE*/
0x00, /*;REG 67, RESERVE*/
0x00, /*;REG 68, RESERVE*/
0x00, /*;REG 69, RESERVE*/
0x00, /*;REG 6a, RESERVE*/
0x00, /*;REG 6b, RESERVE*/
0x00, /*;REG 6c, RESERVE*/
0x00, /*;REG 6d, RESERVE*/
0x00, /*;REG 6e, RESERVE*/
0x00, /*;REG 6f, RESERVE*/
0x00, /*;REG 70, RESERVE*/
0x00, /*;REG 71, RESERVE*/
0x00, /*;REG 72, RESERVE*/
0x00, /*;REG 73, RESERVE*/
0x00, /*;REG 74, RESERVE*/
0x00, /*;REG 75, RESERVE*/
0x00, /*;REG 76, RESERVE*/
0x00, /*;REG 77, RESERVE*/
0x00, /*;REG 78, RESERVE*/
0x00, /*;REG 79, RESERVE*/
0x00, /*;REG 7a, RESERVE*/
0x00, /*;REG 7b, RESERVE*/
0x00, /*;REG 7c, RESERVE*/
0x00, /*;REG 7d, RESERVE*/
0x00, /*;REG 7e, RESERVE*/
0x00, /*;REG 7f, RESERVE*/
0x10, /*;REG 80, task enable and IDQ and backed clock definition*/
0x00, /*;REG 81, RESERVE*/
0x00, /*;REG 82, RESERVE*/
0x01, /*;REG 83, XCLK output phase and X-port output enable*/
0xa0, /*;REG 84, IGPH, IGPV, IGP0, IGP1 output definition*/
0x10, /*;REG 85, Signal ploarity control and I -port byte swaping*/
0x45, /*;REG 86, FIFO flag thresholds and video/text arbitration*/
0x01, /*;REG 87, ICLK and IDQ output phase I-port enable*/
0xca, /*;REG 88, power save control and software reset*/
/*;scaler and audio clock in power down*/
0x00, /*;REG 89, RESERVE*/
0x00, /*;REG 8a, RESERVE*/
0x00, /*;REG 8b, RESERVE*/
0x00, /*;REG 8c, RESERVE*/
0x00, /*;REG 8d, RESERVE*/
0x00, /*;REG 8e, RESERVE*/
0x00, /*;REG 8f, RESERVE*/
0x00, /*;REG 90, task handling*/
0x00, /*;REG 91, scaler input source and format definition*/
0x00, /*;REG 92, reference signal definition at scaler input*/
0x00, /*;REG 93, I-port output formats and configuration*/
0x10, /*;REG 94, XO H input offset*/
0x00, /*;REG 95, XO H input offset*/
0xd0, /*;REG 96, XS LENGTH*/
0x02, /*;REG 97, XS LENGTH*/
0x0a, /*;REG 98, VO*/
0x00, /*;REG 99, VO*/
0xf2, /*;REG 9A, VS*/
0x00, /*;REG 9B, VS*/
0xd0, /*;REG 9C, XD*/
0x02, /*;REG 9D, XD*/
0xf0, /*;REG 9E, VD*/
0x00, /*;REG 9F, VD*/
0x01, /*;REG a0, interger prescale */
0x00, /*;REG a1, accumullation length for prescaler*/
0x00, /*;REG a2, FIR-prefilter and prescaler DC-Normalization */
0x00, /*;REG a3, RESERVE*/
0x80, /*;REG a4, scaler brightness control*/
0x40, /*;REG a5, scaler contrast control*/
0x40, /*;REG a6, scaler saturation control */
0x00, /*;REG a7, RESERVE*/
0x00, /*;REG a8, horizontal scaling increment for luminance*/
0x04, /*;REG a9, horizontal scaling increment for luminance*/
0x00, /*;REG aa, horizontal phase offset*/
0x00, /*;REG ab, RESERVE*/
0x00, /*REG ac, horizontal scaling increment for luminance*/
0x02, /*;REG ad, horizontal scaling increment for luminance*/
0x00, /*;REG ae, horizontal phase offset chrominace*/
0x00, /*;REG af, RESERVE*/
0x00, /*;REG b0, vertical scaling increment for luminance*/
0x04, /*;REG b1, vertical scaling increment for luminance*/
0x00, /*;REG b2, vertical scaling increment for chrominace*/
0x04, /*;REG b3, vertical scaling increment for chrominace*/
0x00, /*;REG b4, vertical scaling mode control*/
0x00, /*;REG b5, reserved*/
0x00, /*;REG b6, RESERVE*/
0x00, /*;REG b7, RESERVE*/
0x00, /*;REG b8, vertical phase offsets luminance and chrominance*/
0x00, /*;REG b9, vertical phase offsets luminance and chrominance*/
0x00, /*;REG ba, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bb, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bc, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bd, vertical phase offsets luminance and chrominance*/
0x00, /*;REG be, vertical phase offsets luminance and chrominance*/
0x00, /*;REG bf, vertical phase offsets luminance and chrominance*/
}; ⌨️ 快捷键说明
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